AD9739BBCZ datasheet(4/50 Pages) AD

4 / 50 page

AD9739

Data Sheet

Rev. E | Page 4 of 50

Deleted Mu Control Operation Section, Search Mode Section,

and Figure 89................................................................................... 41

Moved Figure 64 ............................................................................. 41

Added Peak DAC Output Power Capability Section and Figure 65..41

Deleted Figure 90, Figure 91, Track Mode Section, Mu Delay

and Phase Readback Section, Operating the Mu Controller

Manually Section, and Calculating Mu Delay Line Step Size

Section.............................................................................................. 42

Added Output Stage Configuration Section and Figure 66 to

Figure 70 .......................................................................................... 42

Added Nonideal Spectral Artifacts Section, Figure 71, and

Table 30 ............................................................................................ 43

Deleted Operation in Master Mode, Figure 93, and Figure 94 .......44

Added Lab Evaluation of the AD9739 Section, Power Dissipation

and Supply Domains Section, and Figure 72 to Figure 74 ........ 44

Deleted Figure 95, Operation in Slave Mode Section, and Data

Receiver Operation in Auto Mode Section ................................. 45

Changes to Recommended Start-Up Sequence Section............ 45

Added Figure 75.............................................................................. 45

Deleted Figure 97, Data Receiver Operation in Manual Mode

Section, Calculating the DCI Delay Line Step Size Section, and

Maximum Allowable Data Timing Skew/Jitter Section ............ 46

Added Table 31 ............................................................................... 46

Deleted Optimizing the Clock Common-Mode Voltage Section,

Figure 99, Analog Control Registers Section, Mirror Roll-Off

Frequency Control Section, and Figure 101 ............................... 47

Added Table 32 ............................................................................... 47

Deleted Figure 103, Figure 104, and Figure 106......................... 48

Updated Outline Dimensions....................................................... 48

Deleted Figure 107 to Figure 109 ................................................. 49

Deleted Table 35 to Table 44 ......................................................... 50

7/2011—Rev 0 to Rev A

Changes to Table 2, DAC CLOCK INPUT (DACCLK_P,

DACCLK_N), Added DAC Clock Rate..........................................4

Changes to Table 3, Added Dynamic Performance Parameters .......5

Change to Ordering Guide............................................................ 53

2/2009—Revision 0: Initial Version

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