AD9152-EBZ datasheet(5/103 Pages) AD

5 / 103 page

Data Sheet

AD9152

Rev. B | Page 5 of 103

SPECIFICATIONS

DC SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, PLLVDD12 = 1.2 V,

SVDD12 = 1.2 V, SDVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY

Differential Nonlinearity (DNL)

±5.0

LSB

Integral Nonlinearity (INL)

±10.0

LSB

MAIN DAC OUTPUTS

Gain Error

With internal reference

−5.5

−1.3

+5.5

% FSR

I/Q Gain Mismatch

−4.5

+4.5

% FSR

Full-Scale Output Current (IOUTFS)

Based on a 4 kΩ external resistor between I120 and ground

Maximum Setting

19.1

20.22

21.4

Minimum Setting

3.8

4.04

4.3

Output Compliance Range

2.3

3.47

Output Resistance

MΩ

Output Capacitance

3.0

Gain DAC Monotonicity

Guaranteed

MAIN DAC TEMPERATURE DRIFT

Offset

0.1

ppm/°C

Gain

ppm/°C

Reference Voltage

ppm/°C

REFERENCE

Internal Reference Voltage

0.5

ANALOG SUPPLY VOLTAGES

AVDD33

±5%

3.13

3.3

3.47

PVDD12, CVDD12

±5%

1.14

1.2

1.26

±2%

1.274

1.3

1.326

SVDD12, PLLVDD12, VTT

±5%

1.14

1.2

1.26

±2%

1.274

1.3

1.326

DIGITAL SUPPLY VOLTAGES

DVDD12, SDVDD12

±5%

1.14

1.2

1.26

±2%

1.274

1.3

1.326

SIOVDD33

±5%

3.13

3.3

3.47

IOVDD

±5%

1.71

1.8

3.47

POWER CONSUMPTION

Total Power

2× interpolation mode, fDAC = 1.5 GSPS, IF = 70 MHz, PLL

off, INVSINC on, digital gain on, NCO on, JESD204B

Mode 4, four SERDES lanes with 7.5 Gbps lane rate,

IOUTFS = 20 mA

1223

AVDD33

PVDD12

CVDD12

179

SDVDD12 and SVDD12

(Includes PLLVDD12 and VTT)

328

DVDD12

246

SIOVDD33 and IOVDD

5.7

OPERATING TEMPERATURE RANGE

−40

+25

+85

°C

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