AD9152 datasheet(40/103 Pages) AD

40 / 103 page

AD9152

Data Sheet

Rev. B | Page 40 of 103

Link Delay

The link delay of a JESD204B system is the sum of the fixed and

variable delays from the transmitter, channel, and receiver as

shown in Figure 49.

For proper functioning, all lanes on the link must be read during

the same LMFC period. Section 6.1 of the JESD204B specification

states that the LMFC period must be larger than the maximum

link delay. For the AD9152, this is not necessarily the case; instead,

the AD9152 uses a local LMFC for the link (LMFCRx) that can

be delayed from the SYSREF± aligned LMFC. Because the LMFC

is periodic, this can account for any amount of fixed delay. As a

result, the LMFC period must only be larger than the variation in

the link delays, and the AD9152 can achieve proper performance

with a smaller total latency. Figure 47 and Figure 48 show a case

where the link delay is larger than an LMFC period. Note that it

can be accommodated by delaying LMFCRx.

ILAS

DATA

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

EARLY ARRIVING

LMFC REFERENCE

LATE ARRIVING

LMFC REFERENCE

Figure 47. Link Delay > LMFC Period Example

ILAS

DATA

FRAME CLOCK

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

LMFCRX

LMFC DELAY

LMFC REFERENCE FOR ALL POWER CYCLES

Figure 48. LMFC_DELAY_x to Compensate for Link Delay > LMFC

ILAS

FIXED DELAY

VARIABLE

DELAY

POWER CYCLE

VARIANCE

DATA

LMFC

ALIGNED DATA

AT Rx OUTPUT

DATA AT

Tx INPUT

DATA

DSP

CHANNEL

LOGIC DEVICE

(JESD204B Tx)

JESD204B Rx

DAC

LINK DELAY = DELAYFIXED + DELAYVARIABLE

Figure 49. JESD204B Link Delay = Fixed Delay + Variable Delay

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