TUSB5052 datasheet(46/84 Pages) TI

46 / 84 page

6–6

6.1.5

DMACDR5: DMA-5 Channel Definition Register (P-Port Channel)

This register is used to define the EDB number that the DMA used for data transfer to/from the P-port. In addition,

this register defines the data transfer mode and selects X or Y as the transaction buffer. Note: the transfer direction

is defined by the DIR bit in the PPMCR register.

INE

CNT

XYI

XYO

R/W

BIT

NAME

RESET

FUNCTION

2–0

E[2:0]

End-point descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.

XYO

X/Y- Output buffer select bit

XYO = 0 Next output-buffer to transmit/receive is X.

XYO = 1 Next output-buffer to transmit/receive is Y.

XYI

X/Y- Input buffer sselect bit

XYI = 0

Next input-buffer to transmit/receive is X.

XYI = 1

Next input-buffer to transmit/receive is Y.

CNT

DMA Continuous transfer control bit. This bit defines the mode of the DMA transfer.

CNT = 0

Burst Mode: DMA stops the transfer when the byte-count is zero or when a transfer error occurs. At the

end of transfer, the high to low transition of EN interrupts the MCU (if enabled). In this mode, the XY bit is

set by the MCU to define the current buffer (X or Y).

CNT = 1

Continuous Mode: In this mode, the DMA and UBM alternate between the X and Y buffers. The UBM

sets the XY bit and the DMA uses it for the transfer. DMA alternates between X/Y-buffers and continues

receiving (to X/Y buffer) without MCU intervention. DMA updates the byte-count and sets the NAK-bit in

EDB at the end of packet transfer. When the DMA is stopped by a transaction-timeout (or error condition),

the DMA updates the byte-count and NAK-bit in EDB, and interrupts the MCU (via EN = 0). The UBM

transfers the partial packet to host.

INE

DMA Interrupt enable/disable bit. This bit is used to enable/disable the interrupt on transfer completion.

INE = 0

Interrupt is disabled.

INE = 1

Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition of EN-bit.

(When transfer is completed, EN =0)

DMA channel enable. The MCU sets this bit to start the DMA transfer. When transfer completes, or when terminated

due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if interrupt is enabled) .

EN = 0

DMA is halted. 1 to 0 transition interrupts the MCU (if INE = 1).

EN = 1

Setting this bit starts the DMA transfer.

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