S71PL129JC0BAI9P2 datasheet(111/149 Pages) SPANSION

111 / 149 page

August 30, 2004 pSRAM_Type01_12_A1

pSRAM Type 1

111

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Informatio n

Power Savings Modes (For 16M Page Mode, 32M and 64M Only)

There are several power savings modes.

Partial Array Self Refresh

Temperature Compensated Refresh (64M)

Deep Sleep Mode

Reduced Memory Size (32M, 16M)

The operation of the power saving modes ins controlled by the settings of bits

contained in the Mode Register. This definition of the Mode Register is shown in

Figure 39 and the various bits are used to enable and disable the various low

power modes as well as enabling Page Mode operation. The Mode Register is set

by using the timings defined in Figure xxx.

Partial Array Self Refresh (PAR)

In this mode of operation, the internal refresh operation can be restricted to a

16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is

determined by the respective bit settings in the Mode Register. The register set-

tings for the PASR operation are defined in Table xxx. In this PASR mode, when

ZZ# is active low, only the portion of the array that is set in the register is re-

Figure 38. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH)

Page A ddr es s

(A4 - A 20)

LB#, UB#

WE#

tWP

tCW

tDW

High-Z

Dat a Out

tLBW, tUBW

CE#

Wor d A ddr es s

(A0 - A3 )

tWC

tPWC

tDH

tPDW tPDH

tPDW

tPDH

tAS

tPGMAX

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