S71PL129JC0 datasheet(127/149 Pages) SPANSION

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June 25, 2004 pSRAM_Type02_15A1

Type 2 pSRAM

127

Advance

Informatio n

Notes:

1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22.

tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to

output voltage levels.

At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device

to device interconnection.

tOE(max) is met only when OE# becomes enabled after tAA(max).

If invalid address signals shorter than min. tRC are continuously repeated for over 4µs, the device needs a normal read

timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4µs.

Write Timings

Figure 48. Timing Waveform of Page Cycle (Page Mode Only)

Figure 49. Write Cycle #1 (WE# Controlled)

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Address

Valid

Address

Valid

Address

Valid

Address

Valid

Address

tPC

tPA

High Z

A1~A0

DQ15~DQ0

OE#

tOHZ

tOE

tCO

tAA

CS1#

CS2

Address1)

Address

CS1#

Data Undefined

UB#, LB#

WE#

Data in

Data out

tWC

tCW

tWR

tAW

tBW

tWP

tAS

tDH

tDW

tWHZ

tOW

High-Z

Data Valid

CS2

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