S71GL032A datasheet(22/102 Pages) SPANSION

22 / 102 page

S71GL032A Based MCPs

S71GL032A_00_A0 March 31, 2005

Advance

Info rmation

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or

word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by CE# and OE#.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE#

pins to VIL. CE# is the power control and selects the device. OE# is the output

control and gates array data to the output pins. WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. The device remains enabled for read access until the command register

contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read-Only Op-

erations table for timing specifications and the timing diagram. Refer to the DC

Characteristics table for the active current specification on reading array data.

Page Mode Read

The device is capable of fast page mode read and is compatible with the page

mode Mask ROM read operation. This mode provides faster read access speed for

random locations within a page. The page size of the device is 4 words/8 bytes.

The appropriate page is selected by the higher address bits A(max)–A2. Address

bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word

within a page. This is an asynchronous operation; the microprocessor supplies

the specific word location.

The random or initial page access is equal to tACC or tCE and subsequent page

read accesses (as long as the locations specified by the microprocessor falls

within that page) is equivalent to tPACC. When CE# is deasserted and reasserted

for a subsequent access, the access time is tACC or tCE. Fast page mode accesses

are obtained by keeping the “read-page addresses” constant and changing the

“intra-read page” addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

The device features an Unlock Bypass mode to facilitate faster programming.

Once the device enters the Unlock Bypass mode, only two write cycles are re-

quired to program a word, instead of four. The “Word Program Command

Sequence” section has details on programming data to the device using both

standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 2-Table 17 indicates the address space that each sector occupies.

Refer to the DC Characteristics table for the active current specification for the

write mode. The AC Characteristics section contains timing specification tables

and timing diagrams for write operations.

S71GL032A bảng dữ liệu(PDF) 22 Page - SPANSION

S71GL032A bảng dữ liệu(HTML) 22 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL