ACE24AC02A3C

Two-wire Serial EEPROM

VER 1.1

3

Block Diagram

Pin Description

(A)

Serial Clock (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of

this clock is to clock data out of the EEPROM device.

(B)

Serial Data Line (SDA)

SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can

be wired- OR with other open-drain output devices.

(C)

Device / Chip Select Addresses (A2, A1, A0)

These are the chip select input signals for the serial EEPROM devices. Typically, these signals are

hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL.

(D)

Write Protect (WP)

The ACE24AC02A3C devices have a WP pin to protect the whole EEPROM array from

programming. Programming operations are allowed if WP pin is left un-connected or input to VIL.

Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read

operations is not affected by the WP pin’s input level.