ADF41513 datasheet(22/33 Pages) AD

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ADF41513

Preliminary Technical Data

Rev. PrL | Page 22 of 33

DLD Mode

normal digital lock detect, set Register 5, Bits[31:30] = 0b01.

Other options tristate the pin and force high or low logic levels,

as shown in Figure 26.

CP Current Setting

bits to the charge pump current that the loop filter is designed

for based on the application of the user. The recommended

practice is to design the loop filter for a charge pump current of

2.4 mA or 2.7 mA and then use the programmable charge pump

current to fine tune the loop filter frequency response.

LSB_P1

MOD value. Enabling the 26th bit reduces fractional spurs but

the reduction also adds a fixed fPFD/226 frequency offset to the

output frequency. To disable this frequency offset, set Register

5, Bit 24 = 1.

Prescaler

The dual modulus prescaler (4/5 and 8/9) is set by Register 5,

Bit 23. The prescaler, at the input to the N divider, divides down

the fRFIN signal so that the N divider can work. The prescaler is

based on a synchronous 4/5 core. The prescaler setting affects

the RF frequency and the minimum and maximum INT value

as follows:

•

Prescaler 4/5: 23 ≤ INT ≤ 32771, fRFIN_MAX = 13.25 GHz

•

Prescaler 8/9: 75 ≤ INT ≤ 65535, fRFIN_MAX = 26.5 GHz

RDIV2

the N Divider and R Counter section for more information.

This feature can provide a 50% duty cycle signal to the PFD.

Reference Doubler

N Divider and R Counter section for more information.

R Counter

Divider and R Counter section for more information.

CLK1 Divider

Phase Resync section for more information.

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