PRELIMINARY

12

PRELIMINARY

Rev F

CPC5750

2.1.5 CPB (bit 2)

The Clocks Per Bit (CPB) selection bit is used to set the number of PCM clock cycles per bit of transmit and

receive data transfer at either 1 clock-per-bit or 2 clocks-per-bit. This programmable option is only used in PCM

Mode as the clock rate is auto-detected in GCI Mode.

Logic '0': 1 Clock cycle Per data Bit

Logic '1': 2 Clock cycles Per data Bit

2.1.6 TXZ (bit 1)

impedance.

Logic '0': Tri-State on the first PCLK Rising Edge following the LSB of the time slot.

Logic '1': Tri-State on the PCLK Falling Edge during the LSB of the time slot. (The second falling

edge of PCLK when CPB = 1.)

2.1.7 TM (bit 0)

Reserved: This bit is not user defined and it’s value should not be modified. The default power up and reset value

of this bit is 0 and must not be changed.

2.2 TX Path Gain: ±1dB Steps Register

FIve bits of this register determine the analog input amplifier gain in 1 dB steps as shown in the following table.

2.2.1 TXG (bits [4:0])

TXG is a 5-bit, 2's complement number between -12 and 12. This value sets the transmit path gain in 1 dB

increments. Values of TXG larger than +12 set a gain of +12dB. Values of TXG less than -12 set a gain of -12dB.

2.3 TX Path Gain: +0.1dB Steps Register

Four bits of this register determine the analog input amplifier gain in 0.1 dB steps as shown in the following table.

2.3.1 TXB (bits [3:0])

TXB is a 4-bit number between 0 and +9. This value increases the transmit path gain in 0.1dB increments. These

bits are used in conjunction with the TXG bits to define a 9-bit gain value from -12dB to +12.9dB in 0.1dB steps.

For example, to set the transmit gain to -0.1dB, the TXG bits are set for -1dB (11111) and the TXB bits are set for

+0.9dB (1001). The nine bit value 111111001(binary) provides for a transmit gain = -1dB + 0.9dB = -0.1dB;

EX2: 111110000 = -1dB; EX3: 001110011 = +7.3dB. Values of TXB are always positive and values greater

than 9 continue to define the gain as +0.9dB.

Register

7

6

5

4

3

2

1

0

Address

TX Path Gain: ±1dB Steps

-

-

-

TXG(4)

TXG(3)

TXG(2)

TXG(1)

TXG(0)

0x1

Default Value

0

0000000

-

Register

7

6

5

4

3

2

1

0

Address

TX Path Gain: +0.1dB Steps

----

TXB(3)

TXB(2)

TXB(1)

TXB(0)

0x2

Default Value

0

0000000

-