DM74LS395 datasheet(3/6 Pages) NSC

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Switching Characteristics

VCC ea50V TA ea25 C

Symbol

Parameter

RL e2kX CL e 15 pF

Units

Min

Max

fmax

Maximum Shift Frequency

MHz

tPLH

Propagation Delay

tPHL

CP to On

tPHL

Propagation Delay

MR to On

tPZH

Output Enable Time

tPZL

tPHZ

Output Disable Time

tPLZ

Functional Description

The ‘LS395 contains four D-type edge-triggered flip-flops

and auxiliary gating to select a D input either from a Parallel

(Pn) input or from the preceding stage When the Select

input is HIGH the Pn inputs are enabled A LOW signal in

the S input enables the serial inputs for shift-right opera-

tions as indicated in the Truth Table

State changes are initiated by HIGH-to-LOW transitions on

the Clock Pulse (CP) input Signals on the Pn DS and S

inputs can change when the Clock is in either state provid-

ed that the recommended setup and hold times are ob-

served When the S input is LOW a CP HIGH-LOW tran-

sition transfers data in O0 to O1 O1 to O2 and O2 to O3 A

left-shift is accomplished by connecting the outputs back to

the Pn inputs but offset one place to the left ie O3 to P2

O2 to P1 and O1 to P0 with P3 acting as the linking input

from another package

When the OE input is HIGH the output buffers are disabled

and the O0 – O3 outputs are in a high impedance condition

The shifting parallel loading or resetting operations can still

be accomplished however

Logic Diagram

TLF9833 – 3

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