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CY28329
Document #: 38-07040 Rev. *E
Page 12 of 17
VTTPWRGD# Timing Diagrams
GND VRM 5/12V
PWR_GD
VID [3:0]
BSEL [1:0]
VRM
VCC CPU CORE
VTTPWRGD
VCC CLOCK GEN
0.2–0.3 ms
delay
Wait for
VTTPWRGD#
Sample
BSELS
CLOCK STATE
State 0
State 1
State 2
State 3
ON
OFF
OFF
CLOCK VCO
CLOCK OUTPUTS
Figure 2. CPU Power BEFORE Clock Power
ON
VTTPWRGD FROM
Figure 3. CPU Power AFTER Clock Power
GND VRM 5/12V
PWRGD
VID [3:0]
BSEL [1:0]
PWRGD FROM
VRM
PWRGD# FROM
VCC CPU CORE
VTTPWRGD
VCC CLOCK GEN
0.2–0.3 ms
delay
Wait for
VTTPWRGD#
Sample
BSELS
CLOCK STATE
State 0
State 1
State 2
State 3
OFF
OFF
CLOCK VCO
CLOCK OUTPUTS
ON
ON
NPN
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