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AD9554 bảng dữ liệu(PDF) 20 Page - Analog Devices |
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AD9554 bảng dữ liệu(HTML) 20 Page - Analog Devices |
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20 / 116 page ![]() AD9554 Data Sheet Rev. D | Page 20 of 116 Pin No. Mnemonic Input/ Output Pin Type Description 60, 61, 65, 66, 67 M5, M6, M7, M8, M9 I/O 1.5 V/1.8 V CMOS Configurable Input/Output Pins. These pins are used for status and control of the AD9554. These pins are also used at power-up and reset to determine the serial port and address. See the Multifunction Pins at Reset/Power-Up section for more information about the internal 100 kΩ pull-up or pull-down resistors. These pins are on the VDD digital power domain (Pin 62), and the logic high voltage for this pin matches the voltage of the VDD pins. 63 XOB I Differential input Complementary System Clock Input. Complementary signal to XOA. XOB contains internal dc biasing and must be ac-coupled with a 0.1 μF capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. 64 XOA I Differential input System Clock Input. XOA contains internal dc biasing and must be ac-coupled with a 0.1 μF capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. Single-ended CMOS is also an option, but a spur may be introduced if the duty cycle is not 50%. When using XOA as a single-ended input, connect a 0.1 μF capacitor from XOB to ground. 68 LF_3 I/O Loop filter for APLL_3 Loop Filter Node for the APLL_3. Connect an external 15 nF capacitor from this pin to Pin 69 (LDO_3). 69 LDO_3 I LDO bypass APLL_3 Loop Filter Voltage Regulator. Connect a 0.22 μF capacitor from this pin to ground. This pin is also the ac ground reference for the integrated APLL_3 external loop filter. 72 OUT3B O HCSL, LVDS- compatible, LVPECL- compatible PLL3 Output 3B. This HCSL output can be configured as a LVDS- or LVPECL- compatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. 0 EPAD GND Exposed pad The exposed pad is the ground connection on the chip. It must be soldered to the analog ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. |
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