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AD9547 bảng dữ liệu(PDF) 17 Page - Analog Devices

tên linh kiện AD9547
Giải thích chi tiết về linh kiện  Dual/Quad Input Network Clock Generator/Synchronizer
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AD9547 bảng dữ liệu(HTML) 17 Page - Analog Devices

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Data Sheet
AD9547
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
47
I
Differential
input
REFB
Reference B Input. This internally biased input is typically ac-coupled and,
when configured as such, can accept any differential signal with a single-ended
swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
48
I
Differential
input
REFBB
Complementary Reference B Input. Complementary signal to the input provided
on Pin 47. The user can configure this pin as a separate single-ended input.
51
I
NC
No Connection. This pin should be left floating.
52
O
Logic
IRQ
Interrupt Request Line.
54, 55, 56, 57,
60, 61, 62, 63
I/O
3.3 V CMOS
M0, M1, M2, M3,
M4, M5, M6, M7
Configurable I/O Pins. These pins are configured under program control.
M0 to M2 control the serial port mode selection (see Table 30), and M3 to M7
control the EEPROM loading at startup or reset (see the Initial M0 to M7 Pin
Programming section). Note that there are no internal pull-up or pull-down
resistors on these pins, and the user should place pull-up or pull-down
resistors on each of these pins to avoid unpredictable start-up behavior.
EP
O
Exposed
pad
Exposed pad
The exposed pad must be connected to ground (VSS).
Rev. G | Page 17 of 106



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