AD9545 datasheet(73/157 Pages) AD

73 / 157 page

Data Sheet

AD9545

Rev. A | Page 73 of 157

The frequency translation factor for phase buildout mode is:























 +



MOD

FRAC

REF

OUTx

However, the NCO, VCO, TDCs, and the APLL PFD inputs

each have specific frequency limits. The following formulas

relate fNCO, fVCO, fTDC and fPFD to fREFx, fOUTx, and divider values.

Note that each formula has two solutions: one with respect to

the input frequency (fREFx) and the other with respect to the

output frequency (fOUTx). The user must ensure that fNCO, fVCO,

fTDC and fPFD are within their specified frequency bounds.

fTDC = fREFx/R

= (2 × Q/(M × (N + FRAC/MOD))) × fOUTx

(5)

fNCO = fPFD = (2 × Q/M) × fOUTx

= ((N + FRAC/MOD)/R) × fREFx

(6)

fVCO = 2 × Q × fOUTx

= ((N + FRAC/MOD) × M/R) × fREFx

(7)

When the reference source is auxiliary NCO 0, auxiliary NCO 1, or

the feedback from the other DPLL, then in Euquation 5 through

Equation 6, use R = 1.

INTERNAL ZERO DELAY (HITLESS) MODE

Figure 64 shows the internal zero delay configuration. Internal

zero delay mode is a hitless mode (rather than phase buildout

operating mode), in which the AD9545 gradually changes the

output phase as it realigns to the phase of the new reference.

The user has some control over the magnitude of the output

disturbance via the phase slew limit of the AD9545 and tuning

word clamp features (see the Phase Slew Rate Limit section and

Tuning Word Offset Clamp section, respectively).

In internal zero delay mode, the feedback path of the PLL origi-

nates at the output a user selected Q divider in the output

distribution section. The feedback Q divider selection is via the

5-bit unsigned internal/external zero delay feedback path bit

field (where x is the PLL channel (0 or 1) and y is the profile

number (0 to 5)). The internal/external zero delay feedback path

bit fields reside in Bits[D4:D0] of Register 0x1202, Register 0x1222,

0x12A2, Register 0x1602, Register 0x1622, Register 0x1642,

REFx

TDC

INTERNAL ZERO DELAY

OUTxyN/

OUTxyP

REFX

TDC

AD9545

AUX

NCO 0/NCO 1

TDC

OTHER DPLL

FEEDBACK

TDC

DIGITAL CROSS

POINT MUX

TIME STAMP PROCESSOR,

DIGITAL LOOP FILTER,

TUNING WORD PROCESSOR

AND NCO

FEEDBACK

TDC

PFD

AND

LOOP

FILTER

M-DIVIDER

N-DIVIDER

TDC

OUTPUT

DISTRIBUTION

DPLL

N + FRAC/MOD

MUX

SYSTEM

CLOCK

LFx

XOA XOB

APLL

VCO

÷2

Figure 64. Internal Zero Delay PLL Configuration

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