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AD9530 bảng dữ liệu(PDF) 33 Page - Analog Devices |
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AD9530 bảng dữ liệu(HTML) 33 Page - Analog Devices |
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33 / 41 page  Data Sheet AD9530 Rev. 0 | Page 33 of 41 PART VERSION (REGISTER 0x006) Table 29. Bit Descriptions for PART_VERSION (Default: 0x14) Bits Bit Name Settings Description Reset Access [7:0] PART VERSION The Analog Devices unified SPI protocol reserves this read only register location for identifying the die revision. 0x00 R USER SCRATCH PAD 1 (REGISTER 0x00A) Table 30. Bit Descriptions for USER_SCRATCHPAD1 (Default: 0x00) Bits Bit Name Settings Description Reset Access [7:0] USER_SCRATCHPAD1, Bits[7:0] 0x00 to 0xFF This register has no effect on device operation. It is available for serial port debugging or register setting revision control. There are two additional user scratch pad registers at Address 0x0FE and Address 0x0FF. 0x00 RW SPI VERSION (REGISTER 0x00B) Table 31. Bit Descriptions for SPI_VERSION (Default: 0x00) Bits Bit Name Settings Description Reset Access [7:0] SPI_VERSION, Bits[7:0] The Analog Devices unified SPI protocol reserves this read only register location for identifying the version of the unified SPI protocol. 0x00 R VENDOR ID (REGISTER 0x00C AND REGISTER 0x00D) Table 32. Bit Descriptions for VENDOR ID (Default: 0x56) Bits Bit Name Settings Description Reset Access [7:0] VENDOR_ID, Bits[7:0] The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this device. All Analog Devices parts adhering to the unified serial port specification have the same value in this register. 0x56 R Table 33. Bit Descriptions for VENDOR_ID (Default: 0x04) Bits Bit Name Settings Description Reset Access [7:0] VENDOR_ID, Bits[15:8] The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this part. All Analog Devices parts adhering to the unified serial port specification have the same value in this register. 0x04 R IO_UPDATE (REGISTER 0x00F) Table 34. Bit Descriptions for IO_UPDATE (Default: 0x00) Bits Bit Name Settings Description Reset Access [7:1] RESERVED 0x00 When writing to Register 0x00F, these bits must be 0x0. 0x00 W 0 IO_UPDATE Writing a 1 to this bit transfers the data in the serial input/output buffer registers to the internal control registers of the device. This is a live and autoclearing bit. 0b W R DIVIDER—REFERENCE INPUT DIVIDER (REGISTER 0x010) Table 35. Bit Descriptions for R_DIVIDER (Default: 0x01) Bits Bit Name Settings Description Reset Access [7:0] R_DIVIDER, Bits[7:0] 0x01 to 0xFF PLL reference divider. These bits control the divide ratio of the R divider. Divide ratio goes from ÷1 (by writing 0x01) to ÷255 (by writing 0xFF). 0x01 RW |
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