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AD9528 bảng dữ liệu(PDF) 17 Page - Analog Devices

tên linh kiện AD9528
Giải thích chi tiết về linh kiện  JESD204B Clock Generator with 14 LVDS/HSTL Outputs
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AD9528 bảng dữ liệu(HTML) 17 Page - Analog Devices

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Data Sheet
AD9528
Rev. D | Page 17 of 67
Pin
No.
Mnemonic
Type1
Description
15
LDO_VCO
P/O
2.5 V LDO Internal Regulator Decoupling for the VCO. Connect a 0.47 μF decoupling capacitor from
this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close
proximity to the device.
16
VDD
P
3.3 V Supply for the PLL2 Internal Regulator.
17
NIC
NIC
Not Internally Connected. The pin can be left floating.
18
NIC
NIC
Not Internally Connected. The pin can be left floating.
19
RESET
I
Digital Input, Active Low. Resets internal logic to default states.
20
VDD
P
3.3 V Supply for the PLL2 Internal Regulator.
21
CS
Serial Control Port Chip Select, Active Low. This pin has an internal 35 kΩ pull-up resistor.
22
SCLK/SCL
I
Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming.
23
SDIO/SDA
I/O
Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I2C Mode (SDA).
24
SDO
O
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There
is no internal pull-up or pull-down resistor on this pin.
25
OUT13
O
Square Wave Clocking Output 13.
26
OUT13
O
Complementary Square Wave Clocking Output 13. High speed output up to 1.25 GHz.
27
VDD13
P
3.3 V Supply for the Output 13 Clock Driver. High speed output up to 1.25 GHz.
28
OUT12
O
Square Wave Clocking Output 12. High speed output up to 1.25 GHz.
29
OUT12
O
Complementary Square Wave Clocking Output 12. High speed output up to 1.25 GHz.
30
VDD12
P
3.3 V Supply for the Output 12 Clock Divider.
31
OUT11
O
Square Wave Clocking Output 11.
32
OUT11
O
Complementary Square Wave Clocking Output 11.
33
VDD11
P
3.3 V Supply for the Output 11 Clock Driver.
34
OUT10
O
Square Wave Clocking Output 10.
35
OUT10
O
Complementary Square Wave Clocking Output 10.
36
VDD10
P
3.3 V Supply for the Output 10 Clock Divider.
37
OUT9
O
Square Wave Clocking Output 9.
38
OUT9
O
Complementary Square Wave Clocking Output 9.
39
VDD9
P
3.3 V Supply for the Output 9 Clock Driver.
40
OUT8
O
Square Wave Clocking Output 8.
41
OUT8
O
Complementary Square Wave Clocking Output 8.
42
VDD8
P
3.3 V Supply for the Output 8 Clock Divider.
43
OUT7
O
Square Wave Clocking Output 7.
44
OUT7
O
Complementary Square Wave Clocking Output 7.
45
VDD7
P
3.3 V Supply for the Output 7 Clock Driver.
46
OUT6
O
Square Wave Clocking Output 6.
47
OUT6
O
Complementary Square Wave Clocking Output 6.
48
VDD6
P
3.3 V Supply for the Output 6 Clock Divider.
49
OUT5
O
Square Wave Clocking Output 5.
50
OUT5
O
Complementary Square Wave Clocking Output 5.
51
VDD5
P
3.3 V Supply for the Output 5 Clock Driver.
52
OUT4
O
Square Wave Clocking Output 4.
53
OUT4
O
Complementary Square Wave Clocking Output 4.
54
VDD4
P
3.3 V Supply for the Output 4 Clock Divider.
55
STATUS0/SP0
I/O
Lock Detect and Other Status Signals/I2C Address. This pin has an internal 30 kΩ pull-down resistor.
56
STATUS1/SP1
I/O
Lock Detect and Other Status Signals/I2C Address. This pin has an internal 30 kΩ pull-down resistor.
57
SYSREF_REQ
I
SYSREF Request Input Logic Control.
58
OUT3
O
Square Wave Clocking Output 3.
59
OUT3
O
Complementary Square Wave Clocking Output 3. High speed output up to 1.25 GHz.
60
VDD3
P
3.3 V Supply for the Output 3 Clock Driver. High speed output up to 1.25 GHz.
61
OUT2
O
Square Wave Clocking Output 2. High speed output up to 1.25 GHz.
62
OUT2
O
Complementary Square Wave Clocking Output 2. High speed output up to 1.25 GHz.
63
VDD2
P
3.3 V Supply for the Output 2 Clock Divider.



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