LTC6955 datasheet(20/22 Pages) AD

20 / 22 page

LTC6955

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

TYPICAL APPLICATIONS

Generation of 7.25GHz, 52fs ADC SNR Jitter Clocks Using LTC6952 and LTC6955-1

49.9Ω

1µF

49.9Ω

100Ω

0.1µF

10k

160Ω

100Ω

1µF

63Ω

1nH

10nF

63Ω

500nF

100Ω

0.1µF

6.8nF

1pF

VCO+

VCO–

REF+

REF–

VOUT

VREF

VCP

3.3V

VVCO

OUT10±

LTC6952

OUT4±

OUT5±

OUT6±

OUT7±

Crystek

CVCO55XT-

7250-7250

IN+

IN–

VOUT

3.3V

VTUNE

VIN

OUT0±

7.25GHz

CLOCKS

OUT1±

OUT2±

OUT10+

OUT10–

LTC6955-1

BUFFER

OUT3±

OUT4±

OUT5±

OUT6+

OUT6–

OUT7±

OUT8+

OUT8–

OUT9±

3.3V

VOUT

+ (PIN 6)

FILT

fVCO

POWERED DOWN OR

ADDITIONAL 7.25GHZ CLOCKS

ADJUST LTC6952 ADEL

REGISTERS TO ALIGN

SYSREF PAIRS TO

LTC6955-1 CLOCKS

OUT8+

OUT8–

OUT0±

OUT9+

OUT9–

CAN BE USED AS

CLOCKS ≤ 3.625GHZ

OR SYSREFS

fOUT = 3.625GHz

SEL3

SEL2

SEL1

SEL0

3.3V

MMZ0603

Crystek

CCHD-575-25-125

125MHz Ref Osc

EZS_SRQ+

EZS_SRQ–

TO SYNC OUTPUTS:

TOGGLE SSYNC REGISTER BIT

6955 TA02a

OUT1±

OUT2±

OUT3±

LTC6955–1 RMS JITTER = 52fs

LTC6952 RMS JITTER = 93fs

EQUIVALENT ADC SNR METHOD

3.625GHz (LTC6952)

7.25GHz (LTC6955–1)

OFFSET FREQUENCY (Hz)

10k

100k

10M 40M

–170

–160

–150

–140

–130

–120

–110

–100

6955 TAO2b

SYSREF VALID

CLOCK EDGE

LTC6952

SYSREF

LTC6955–1

CLOCK

LTC6952 DIE TEMP (TJ)

100°C, ADEL=1

25°C, ADEL=6

–40°C, ADEL=9

TIME (ps)

–500

–250

250

500

–400

400

–400

400

6955 TAO2c

LTC6955-1 and LTC6952

Phase Noise fVCO = 7.25GHz

7.25GHz JESD204B

CLK to SYSREF Alignment

Calibration Over Temperature

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