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21

HMC987LP5E

v03.1112

LOW NOISE 1:9 FANOUT BUFFER

DC - 8 GHz

An example of the two cycle procedure to read from any random address is as follows:

the Master (host), on the irst 9 falling edges of sClk places 9 bit data, d8:d0, Msb irst, on sDi as shown in

a.

the slave () shifts in data on sDi on the irst 9 rising edges of sClk

b.

Master places 4 bit register address , r3:r0, ( the address the WritE ADDrEss register), Msb irst, on the

next 4 falling edges of sClk (10-13). r3:r0=0000.

c.

slave shifts the register bits on the next 4 rising edges of sClk (10-13).

d.

Master places 3 bit chip address, a2:a0, Msb irst, on the next 3 falling edges of sClk (14-16). the chip

address is ixed at 001.

e.

slave shifts the chip address bits on the next 3 rising edges of sClk (14-16).

f.

Master asserts sEn after the 16th rising edge of sClk.

g.

slave registers the sDi data on the rising edge of sEn.

h.

Master clears sEn to complete the address transfer of the two part rEAD cycle.

i.

if we do not wish to write data to the chip at the same time as we do the second cycle , then it is

recommended to simply rewrite the same contents on sDi to register zero on the rEAD back part of the

cycle.

j.

Master places the same sDi data as the previous cycle on the next 16 falling edges of sClk.

k.

slave () shifts the sDi data on the next 16 rising edges of sClk.

l.

sClk.

m. Master asserts sEn after the 16th rising edge of sClk to complete the cycle.

note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the sDo output to prevent a possible

bus contention issue.

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