AD9513

Data Sheet

Rev. B | Page 12 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VS

OUT1

OUT1B

VS

VS

OUT2

OUT2B

VS

VS

CLK

CLKB

VS

SYNCB

VREF

S10

S9

NOTES

1. EXPOSED PADDLE. THE EXPOSED PADDLE ON THIS PACKAGE

IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL

ENHANCEMENT. FOR THE DEVICE TO FUNCTION PROPERLY,

THE PADDLE MUST BE SOLDERED TO A PCB LAND THAT

FUNCTIONS AS BOTH A HEAT DISSIPATION PATH AS WELL

AS AN ELECTRICAL GROUND.

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

AD9513

TOP VIEW

(Not to Scale)

Figure 5. 32-Lead LFCSP Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 4 ,17 ,20, 21,

24, 26, 29, 30

VS

Power Supply (3.3 V).

2

CLK

Clock Input.

3

CLKB

Complementary Clock Input.

5

SYNCB

Used to Synchronize Outputs.

6

VREF

7 to16, 25

S10 to S1, S0

left NC (no connection).

18

OUT2B

Complementary LVDS/Inverted CMOS Output.

19

OUT2

LVDS/CMOS Output.

22

OUT1B

Complementary LVDS/Inverted CMOS Output.

23

OUT1

LVDS/CMOS Output.

27

OUT0B

Complementary LVDS/Inverted CMOS Output.

28

OUT0

LVDS/CMOS Output.

31

GND

Ground. The exposed paddle on the back of the chip is also GND.

32

RSET

Current Set Resistor to Ground. Nominal value = 4.12 kΩ.

EPAD

Exposed Paddle. The exposed paddle on this package is an electrical connection as well as a thermal

enhancement. For the device to function properly, the paddle must be soldered to a PCB land that

functions as both a heat dissipation path as well as an electrical ground.