TDA9554PS datasheet(32/125 Pages) PHILIPS

32 / 125 page

2000 Jun 22

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Teletext decoder with

embedded

µ-Controller

TDA955X/6X/8X PS/N1 series

To enter Stand-by mode, the STAND-BY bit in the

ROMBANK register must be set. Once in Stand-By, the

XTAL oscillator continues to run, but the internal clock to

Acquisition and Display are gated out. However, the clocks

to the 80c51 CPU Core, Memory Interface, I2C,

Timer/Counters, WatchDog Timer and Pulse Width

Modulators are maintained. Since the output values on

RGB and VDS are maintained the display output must be

disabled before entering this mode.

This mode may be used in conjunction with both Idle and

Power-Down modes. Hence, prior to entering either Idle or

Power-Down, the STAND-BY bit may be set, thus allowing

wake-up of the 80c51 CPU core without fully waking the

entire device (This enables detection of a Remote Control

source in a power saving mode).

IDLE MODE

During Idle mode, Acquisition, Display and the CPU

sections of the device are disabled. The following

functions remain active:-

• Memory Interface

• I2C

• Timer/Counters

• WatchDog Timer

• SAD & PWMs

To enter Idle mode the IDL bit in the PCON register must

be set. The WatchDog timer must be disabled prior to

entering Idle to prevent the device being reset. Once in Idle

mode, the XTAL oscillator continues to run, but the internal

clock to the CPU, Acquisition and Display are gated out.

However, the clocks to the Memory Interface, I2C,

Timer/Counters, WatchDog Timer and Pulse Width

Modulators are maintained. The CPU state is frozen along

with the status of all SFRs, internal RAM contents are

maintained, as are the device output pin values. Since the

output values on RGB and VDS are maintained the

Display output must be disabled before entering this

mode.

There are three methods available to recover from Idle:-

• Assertion of an enabled interrupt will cause the IDL bit to

be cleared by hardware, thus terminating Idle mode.

The interrupt is serviced, and following the instruction

RETI, the next instruction to be executed will be the one

after the instruction that put the device into Idle mode.

• A second method of exiting Idle is via an Interrupt

generated by the SAD DC Compare circuit. When

Painter is configured in this mode, detection of an

analogue threshold at the input to the SAD may be used

to trigger wake-up of the device i.e. TV Front Panel

Key-press. As above, the interrupt is serviced, and

following the instruction RETI, the next instruction to be

executed will be the one following the instruction that put

the device into Idle.

• The third method of terminating Idle mode is with an

external hardware reset. Since the oscillator is running,

the hardware reset need only be active for two machine

cycles (24 clocks at 12MHz) to complete the reset

operation. Reset defines all SFRs and Display memory

to a pre-defined state, but maintains all other RAM

values. Code execution commences with the Program

Counter set to ’0000’.

POWER DOWN MODE

In Power Down mode the XTAL oscillator still runs, and

differential clock transmitter is active. The contents of all

SFRs and Data memory are maintained, however, the

contents of the Auxiliary/Display memory are lost. The port

pins maintain the values defined by their associated SFRs.

Since the output values on RGB and VDS are maintained

the Display output must be made inactive before entering

Power Down mode.

The power down mode is activated by setting the PD bit in

the PCON register. It is advised to disable the WatchDog

timer prior to entering Power down. Recovery from

Power-Down takes several milli-seconds as the oscillator

must be given time to stabilise.

There are three methods of exiting power down:-

• An External interrupt provides the first mechanism for

waking from Power-Down. Since the clock is stopped,

external interrupts needs to be set level sensitive prior to

entering Power-Down. The interrupt is serviced, and

following the instruction RETI, the next instruction to be

executed will be the one after the instruction that put the

device into Power-Down mode.

• A second method of exiting Power-Down is via an

Interrupt generated by the SAD DC Compare circuit.

When Painter is configured in this mode, detection of a

certain analogue threshold at the input to the SAD may

be used to trigger wake-up of the device i.e. TV Front

Panel Key-press. As above, the interrupt is serviced,

and following the instruction RETI, the next instruction to

be executed will be the one following the instruction that

put the device into Power-Down.

• The third method of terminating the Power-Down mode

is with an external hardware reset. Reset defines all

SFRs and Display memory, but maintains all other RAM

values. Code execution commences with the Program

Counter set to ’0000’.

TDA9554PS bảng dữ liệu(PDF) 32 Page - NXP Semiconductors

TDA9554PS bảng dữ liệu(HTML) 32 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL