ICS8535I-21

LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER

IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER

8

ICS8535AGI-21 REV. A NOVEMBER 24, 2008

Application Information

Recommendations for Unused Input and Output Pins

Inputs:

CLK Inputs

For applications not requiring the use of a clock input, it can be left

floating. Though not required, but for additional protection, a 1k

Ω

resistor can be tied from the CLK input to ground.

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

Outputs:

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

Ω

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal

distortion. Figures 2A and 2B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and

clock component process variations.

Figure 2A. 3.3V LVPECL Output Termination

Figure 2B. 3.3V LVPECL Output Termination

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN