© PLX Technology, www.plxtech.com

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10/20/2010, Version 1.0

PEX 8748, PCI Express Gen 3 Switch, 48 Lanes, 12 Ports

CPU

CPU

Primary Host

Primary Host

Root

Complex

Root

Complex

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

PEX 8748

PEX 8748

NT

CPU

CPU

Secondary Host

Secondary Host

Non-Transparent

Port

Figure 3. Non-Transparent Port

CPU

CPU

Primary Host

Primary Host

CPU

CPU

Primary Host

Primary Host

Root

Complex

Root

Complex

Root

Complex

Root

Complex

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

PEX 8748

PEX 8748

NT

CPU

CPU

Secondary Host

Secondary Host

CPU

CPU

Secondary Host

Secondary Host

Non-Transparent

Port

Figure 3. Non-Transparent Port

PE

X 8748

PEX 8748

PEX 8748

Figure 4a. Multi-Host

Host 1

Host 1

Host 1

Host 1

Host 2

Host 2

Host 2

Host 2

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

Figure 4b. Multi-Host Fail-Over

Host 1

Host 1

Host 1

Host 1

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

End

Point

Host 2

Host 2

Host 2

Host 2

The PEX 8748 can also be configured in Multi-Host mode

where users can choose up to six ports as host/upstream

ports and assign a desired number of downstream ports to

each host. In Multi-Host mode, a virtual switch is created

for each host port and its associated downstream ports

inside the device. The traffic between the ports of a virtual

switch is completely isolated from the traffic in other

virtual switches. Figure 2 illustrates some configurations

of the PEX 8748 in Multi-Host mode where each ellipse

represents a virtual switch inside the device.

The PEX 8748

also provides

several ways to

configure its

registers. The

device can be

configured

through strapping

pins, I

interface, host

software, or an

optional serial

EEPROM. This

allows for easy

debug during the

development

phase, p

and driver or software upgrade.

erformance m

ual-Host & Failover Support

Non-

or

e

ess

used to send interrupts between the

both CPUs) allow inter-processor communication (see

Figure 3).

am host ports, each with its own dedicated

nfigured for 1+1

al

wo

Hot Plug for High Availability

Hot plug capability allows users to replace hardware

modules and perform maintenance without powering down

ability feature

m ports

t of its

-plug

lly

ompliant with the PCIe power management specification

to

em.

I Express Base Specification r2.0, and is backwards

press Base Specification r1.1 and

onitoring during the operation phase,

D

In Single-Host mode, the PEX 8748 supports a

Transparent (NT) Port, which enables the

implementation of

dual-host systems f

redundancy and host

failover capability. Th

NT port allows systems

to isolate host memory

domains by presenting

the processor subsystem

as an endpoint rather than

another memory

system. Base addr

registers are used to

translate addresses;

doorbell registers are

address domains; and scratchpad registers (accessible by

Multi-Host & Failover Support

In Multi-Host mode, PEX 8748 can be configured with up

to six upstre

downstream ports. The device can be co

redundancy or N+1 redundancy. The PEX 8748 allows the

hosts to communicate their status to each other via speci

door-bell registers. In failover mode, if a host fails, the

host designated for failover will disable the upstream port

attached to the failing host and program the downstream

ports of that host to its own domain. Figure 4a shows a t

host system in Multi-Host mode with two virtual switches

inside the device and Figure 4b shows Host 1 disabled

after failure and Host 2 having taken over all of Host 1’s

end-points.

the system. The PEX 8748 hot plug cap

makes it suitable for High Availability (HA)

applications. Three downstream ports include a Standard

Hot Plug Controller. If the PEX 8748 is used in an

application where one or more of its downstrea

connect to PCI Express slots, each port’s Hot Plug

Controller can be used to manage the hot-plug even

associated slot. Every port on the PEX 8748 is equipped

with a hot-plug control/status register to support hot

capability through external logic via the I

SerDes Power and Signal Management

The PEX 8748 provides low power capability that is fu

c

and supports software control of the SerDes outputs

allow optimization of power and signal strength in a

system. Furthermore, the SerDes block supports loop-back

modes and advanced reporting of error conditions,

which enables efficient management of the entire syst

Interoperability

The PEX 8748 is designed to be fully compliant with the

PC

compatible to PCI Ex

Figure 2. Multi-Host Port Configurations

PEX 8748

PEX 8748

PEX 8748

PEX 8748

x8

4 x4

x8

PEX 8748

PEX 8748

PEX 8748

PEX 8748

x8

3 x4

2 x4

x4

x4

3 x4

4 x4

PEX 8748

PEX 8748

PEX 8748

PEX 8748

8 x4s

4 x4s

PEX 8748

PEX 8748

PEX 8748

PEX 8748

9 x4s

3 x4s