LPC810M021FN8 datasheet(27/78 Pages) NXP

27 / 78 page

LPC81XM

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Product data sheet

Rev. 4.6 — 4 April 2018

27 of 78

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

8.20.6.3

Deep-sleep mode

In Deep-sleep mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if

selected. The IRC output is disabled. In addition all analog blocks are shut down and the

flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog

oscillator and the BOD circuit running for self-timed wake-up and BOD protection.

The LPC81xM can wake up from Deep-sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave mode).

Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Deep-sleep mode saves power and allows for short wake-up times.

8.20.6.4

Power-down mode

In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

clock sources are off except for watchdog oscillator or low-power oscillator if selected. In

addition all analog blocks and the flash are shut down. In Power-down mode, the

application can keep the watchdog oscillator and the BOD circuit running for self-timed

wake-up and BOD protection.

The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave mode).

Any interrupt used for waking up from Power-down mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Power-down mode reduces power consumption compared to Deep-sleep mode at the

expense of longer wake-up times.

8.20.6.5

Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

pin and the self wake-up timer if enabled. Four general-purpose registers are available to

store information during Deep power-down mode. The LPC81xM can wake up from Deep

power-down mode via the WAKEUP pin, or without an external signal by using the

time-out of the self wake-up timer (see Section 8.18).

The LPC81xM can be prevented from entering Deep power-down mode by setting a lock

bit in the PMU block. Locking out Deep power-down mode enables the application to keep

the watchdog timer or the BOD running at all times.

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