WM8950 datasheet(13/52 Pages) WOLFSON

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Preliminary Technical Data

WM8950

PTD Rev 2.1 June 2005

However, a PLL is also included which may be used to generate the internal master clock frequency

in the event that this is not available from the system controller. This PLL uses an input clock,

typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not

required for generation of these clocks, it can be reconfigured to generate alternative clocks which

may then be output on the CSB/GPIO pin and used elsewhere in the system.

POWER CONTROL

The design of the WM8950 has given much attention to power consumption without compromising

performance. It operates at low supply voltages, and includes the facility to power off any unused

parts of the circuitry under software control, includes standby and power off modes.

INPUT SIGNAL PATH

The WM8950 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These

inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA

block which then feeds into a gain boost/mixer stage.

MICROPHONE INPUTS

The WM8950 can accommodate a variety of microphone configurations including single ended and

differential inputs.

The inputs through the MICN, MICP and optionally AUX pins are amplified

through the input PGA as shown in Figure 6 .

A pseudo differential input is the preferential configuration where the positive terminal of the input

PGA is

connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground

should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when

AUX2INPPGA=1) input pins.

Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set

to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting

MICP2INPPGA to 0.

Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic

input)

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