Connection Diagram

20083522

DAP = GND

(Top View)

Pin Descriptions

Pin No.

Symbol

Description

ANALOG I/O

16

A0

Analog input 0. This signal can range from 0V to V

15

A1

Analog input 1. This signal can range from 0V to V

14

A2

Analog input 2. This signal can range from 0V to V

13

A3

Analog input 3. This signal can range from 0V to V

12

A4

Analog input 4. This signal can range from 0V to V

11

A5

Analog input 5. This signal can range from 0V to V

10

A6

Analog input 6. This signal can range from 0V to V

9

A7

Analog input 7. This signal can range from 0V to V

2V

REF

Analog reference voltage input. V

≤ V

+2.7V to +5.5V source (not directly to V

monolithic capacitors located within 1 cm of the V

DIGITAL I/O

6

TDI

Test Data Input to support IEEE 1149.1 features

5

TDO

Test Data Ouput to support IEEE 1149.1 features

7

TMS

Test Mode Select to support IEEE 1149.1 features

8

TCK

Test Clock to support IEEE 1149.1 features

4

TRST

Test Reset to support IEEE 1149.1 features

POWER SUPPLY

1,3

V

DD

Positive supply pin. These pins should be connected to a quiet +2.7V to +5.5V source and

bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the

power pin.

(Note 1)

GND

Ground reference for CMOS circuitry. DAP is the exposed metal contact at the bottom of the

LLP package. The DAP is used as the primary GND connection to the device. It should be

connected to the ground plane with at least 4 vias for optimal low-noise and thermal

performance.

Note 1: Note that GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package.

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2