PI7C21P100 datasheet(9/77 Pages) PERICOM

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PI7C21P100

2-PORT PCI-X BRIDGE

ADVANCE INFORMATION

Page 9 of 77

June 10, 2005 Revision 1.06

DESCRIPTION

The PI7C21P100 is a 2-port PCI-X 2.0 Bridge designed to be compliant with the PCI-X

Addendum to the Local Bus Specification Revision 1.0a. The PI7C21P100 is able to handle

64-bit data at a maximum bus frequency of 133MHz. The PI7C21P100 is designed for high

speed applications such as Ethernet, SCSI, and Fibre Channel. The PI7C21P100 may also be

used for bus expansion, frequency isolations/translations, or PCI-X to PCI

isolations/translations.

FEATURES

INDUSTRY STANDARDS COMPLIANCE

PCI-X Addendum to the Local Bus Specification Revision 1.0a (Mode 1 only)

PCI Local Bus Specification Revision 2.2

PCI-to-PCI Bridge Architecture Specification Revision 1.1

PCI Power Management Interface Specification Revision 1.1

•

Supports D0 and D3 power states

INTERFACE

3.3V signaling with 5V tolerance

133MHz / 64-bit operation on both buses

Dual address cycle support

Concurrent primary and secondary bus operation

Primary and secondary may be run in either PCI mode or PCI-X Mode 1

Asynchronous operation support

Programmable internal arbiter with support for up to 6 external masters on the

secondary bus

•

Internal arbiter may be disabled to use an external arbiter

IEEE 1149.1 JTAG support

OPERATION

Type 0 and Type 1 configuration support

Configuration register access from both primary and secondary buses

2KB of buffering for upstream memory burst read commands

2KB of buffering for downstream memory burst read commands

1KB of buffering for upstream posted memory write commands

1KB of buffering for downstream posted memory write commands

Support for up to 8 active transactions in each direction

ADDITIONAL FEATURES

Capabilities pointer

Ability to define an opaque memory address

Definable base address register

Secondary side PCI-X device privatization

PACKAGING

304-pin PBGA, 31 x 31 mm

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