9

PS8683B

10/17/03

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PI6CVF857

1:10 PLL Clock Driver for

2.5V DDR-SDRAM Memory

Figure 2. Output Load Test Circuit 1

Figure1.IBISModelOutputLoad

VDD

R=60

Ω

VCLK

R=60

Ω

VCLK

VDD/2

GND

VDDQ

Z=60

Ω

C=14pF

R=120

Ω

Z=60

Ω

GND

GND

R=1M

Ω

PROBE

C=14pF

C=1pF

R=1M

Ω

C=1pF