Advanced Clock Drivers Devices

Freescale Semiconductor

9

MPC9331

=1.31 V

At the load end, the voltage will double due to the near

unity reflection coefficient, to 2.6 V. It will then increment

towards the quiescent 3.0 V in steps separated by one round

trip delay (in this case 4.0 ns).

1.

Final skew data pending specification.

Figure 5. Single versus Dual Line

Termination Waveforms

Since this step is well above the threshold region it will not

cause any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines, the

situation in should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance, the line impedance

is perfectly matched.

Figure 6. Optimized Dual Line Termination

Time (ns)

3.0

2.5

2.0

1.5

1.0

0.5

0

24

68

10

12

14

OutB

OutA

In

14

Ω + 22Ω || 22Ω = 50Ω || 50Ω

25

Ω = 25Ω

14

Ω

MPC9331

Output

Buffer

Pulse

Generator

Z = 50

Ω

MPC9931 DUT