SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016

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Freescale Semiconductor, Inc.

The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:

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VPU—Video Processing Unit

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IPUv3H—Image Processing Unit version 3H (2 IPUs)

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GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4

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GPU2Dv2—2D Graphics Processing Unit (BitBlt)

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GPUVG—OpenVG 1.1 Graphics Processing Unit

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ASRC—Asynchronous Sample Rate Converter

Security functions are enabled and accelerated by the following hardware:

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ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)

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SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or

blocking the access to the system debug features.

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CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM

and True and Pseudo Random Number Generator (NIST certified)

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SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock

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CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be

configured during boot and by eFUSEs and will determine the security level operation mode as

well as the TZ policy.

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A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ

initialization.

1.2.2. PF0100Z Features

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Input voltage range to PMIC: 2.8 - 4.5 V

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Buck regulators

— Four to six channel configurable

– SW1A/B/C, 4.5 A (single); 0.3 to 1.875 V

– SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 to 1.875 V

– SW2, 2.0 A; 0.4 to 3.3 V

– SW3A/B, 2.5 A (single/dual); 0.4 to 3.3 V

– SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V

– SW4, 1.0 A; 0.4 to 3.3 V

– SW4, VTT mode provide DDR termination at 50% of SW3A

— Dynamic voltage scaling

— Modes: PWM, PFM, APS