SCF5250EC datasheet(28/56 Pages) NXP

28 / 56 page

SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

Figure 5 and Table 23 provide the timing diagram and timing parameters for the Debug AC.

Figure 5. Debug AC Timing Definition Diagram

HIZ to High Impedance

–

tbd

HIZ to Low Impedance

–

tbd

1 AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output pins. If this value is different,

the input and output timing specifications would need to be adjusted to match the clock load.

2 Outputs (8mA): DATA[31:16], ADDR[25,23:9]

3 Outputs (4mA): SDRAS, SDCAS, SDWE, SD_CS0, SDUDQM, SDLDQM, BCLKE

4 High Impedance (Three-State): DATA[31:16]

Table 23. Debug AC Timing Specification1

1 AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is different, the input and

output timing specifications would need to be adjusted to match the clock load.

Num

Characteristic

Min

Max

Units

PSTCLK to signal Valid (Output valid)

–

PSTCLK to signal Invalid (Output hold)

1.8

–

D32

2 DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is

required.

Signal Valid to PSTCLK (Input setup)

–

PSTCLK to signal Invalid (Input hold)

–

Table 22. Output AC Timing Specification (continued)

Num

Characteristic1

Min

Max

Units

PSTCLK

DSCLK

DSI

PST[3:0]

DDATA[3:0]

DSO

SCF5250EC bảng dữ liệu(PDF) 28 Page - NXP Semiconductors

SCF5250EC bảng dữ liệu(HTML) 28 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL