PEX 8717, PCI Express Gen 3 Switch, 16 Lanes, 10 Ports

© PLX Technology, www.plxtech.com

Page 1 of 5

8/1/2011, Version 1.0

Highlights

o 16-lane, 10-port PCIe Gen 3 switch

- Integrated 8.0 GT/s SerDes

o Typical Power: 4.9 Watts

o Native x2 support

o Standards Compliant

- PCI Express Base Specification, r3.0

(compatible w/ PCIe r1.0a/1.1 & 2.0)

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

o High Performance



performancePAK

 Read Pacing (bandwidth throttling)

 Multicast

 Dynamic Buffer/FC Credit Pool

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 138ns max packet

latency (x4 to x4)

- 2KB Max Payload Size

o Integrated DMA Engine

- Four DMA Channels

- Internal Descriptor Support

- DMA function independent from

transparent switch function

- 64-bit Addressing

- Pre-fetch Descriptor Mode

- Stride Mode

o Multi-Host & Fail-Over Support

- 2 Configurable Non-Transparent ports

- Failover with Non-Transparent port

- Up to 2 upstream/Host ports with 1+1

failover to other upstream port

o Quality of Service (QoS)

- Two Virtual Channels

- Eight traffic classes per port

- Weighted round-robin source

port arbitration

o Reliability, Availability, Serviceability

 visionPAK

 Per Port Performance Monitoring

 SerDes Eye Capture

 PCIe Packet Generator

 Error Injection and Loopback

- 3 Hot Plug Ports with native HP Signals

- SSC Isolation on up to 4 ports

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- Advanced Error Reporting

- Port Status bits and GPIO available

- JTAG AC/DC boundary scan

The ExpressLane™ PEX 8717 device offers Multi-Host PCI Express

switching capability enabling users to connect multiple hosts to their

respective

endpoints

via

scalable,

high

bandwidth,

non-blocking

interconnection to a wide variety of applications including servers, storage,

communications, and graphics platforms. The PEX 8717 is well suited for

fan-out, aggregation, and peer-to-peer traffic patterns.

Multi-Host Architecture

The PEX 8717 employs an enhanced version of PLX’s field tested PEX 8716

PCIe switch architecture, which allows users to configure the device in legacy

single-host mode or multi-host mode with up to two host ports capable of 1+1

(one active & one backup) host failover. This powerful architectural

enhancement enables users to build PCIe based systems to support high-

availability, failover, redundant, or clustered systems.

High Performance & Low Packet Latency

The PEX 8717 architecture supports packet cut-thru with a maximum

latency of 138ns (x4 to x4). This, combined with large packet memory,

flexible common buffer/FC credit pool and non-blocking internal switch

architecture, provides full line rate on all ports for performance-hungry

applications such as servers and switch fabrics. The low latency enables

applications to achieve high throughput and performance. In addition to low

latency, the device supports a packet payload size of up to 2048 bytes,

enabling the user to achieve even higher throughput.

Integrated DMA Engine

The PEX 8717 boasts a versatile and powerful built-in DMA engine. The

DMA engine removes the burden of having to move data between devices

away from the processor – allowing the processor to perform computational

tasks instead. The four DMA channels can support high data rate transfers

between I/O devices connected to any of the switch’s ports. Additionally, the

DMA engine in the PEX 8717 can be used to complement the DMA engine in

the processor by providing additional DMA channels for higher performance.

Data Integrity

The PEX 8717 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction circuitry

throughout the internal data paths as packets pass through the switch.

Flexible Configuration

The PEX 8717’s 10 ports can be

configured to lane widths of x1, x2, x4,

or x8. Flexible buffer allocation, along

with the device's flexible packet flow

control,

maximizes

throughput

for

applications where more traffic flows in

the downstream, rather than upstream,

direction. Any port can be designated as

the upstream port, which can be changed

dynamically. Figure 1 shows some of the

PEX 8717’s common port configurations

in legacy Single-Host mode.