PEX 8712, PCI Express Gen 3 Switch, 12 Lanes, 3 Ports

© PLX Technology, www.plxtech.com

Page 3 of 5

10/7/2010, Version 1.0

switches undergo thorough interoperability testing in

PLX’s Interoperability Lab and compliance testing

the PCI-SIG plug-fest.

performancePAK

™

at

o mancePAK is a suite of unique

feature allows users to throttle the

long

link

ead

Multicast

t feature enables the copying of data (packets)

al-

s,

o

Dynamic Buffer Pool

ic buffer pool for Flow

the

rs

visionPAK

lusive, visionPAK is a debug diagnostics

nce Monitoring

mance monitoring allows

all

SerDes Eye Capture

tem’s signal integrity at the

e

.

Exclusive to PLX, perf r

and innovative performance features which allows PLX’s

Gen 2 switches to be the highest performing Gen 2

switches in the market today. The performancePAK

features consists of the Read Pacing, Multicast, and

Dynamic Buffer Pool.

Read Pacing

The Read Pacing

amount of read requests being made by downstream

devices. When a downstream device requests several

reads back-to-back, the Root Complex gets tied up in

serving that downstream port. If that port has a narrow

and is therefore slow in receiving these read packets from

the Root Complex, then other downstream ports may

become starved – thus, impacting performance. The R

Pacing feature enhances performances by allowing for the

adequate servicing of all downstream devices.

The Multicas

from one ingress port to both egress ports in one

transaction allowing for higher performance in du

graphics, storage, security, and redundant application

among others. Multicast relieves the CPU from having t

conduct multiple redundant transactions, resulting in

higher system performance.

The PEX 8712 employs a dynam

Control (FC) management. As opposed to a static buffer

scheme which assigns fixed, static buffers to each port,

PLX’s dynamic buffer allocation scheme utilizes a

common pool of FC Credits which are shared by other

ports. This shared buffer pool is fully programmable by

user, so FC credits can be allocated among the ports as

needed. Not only does this prevent wasted buffers and

inappropriate buffer assignments, any unallocated buffe

remain in the common buffer pool and can then be used

for faster FC credit updates.

™

Another PLX exc

suite of integrated hardware and software instruments that

users can use to help bring their systems to market faster.

visionPAK features consist of Performance Monitoring,

SerDes Eye Capture, Error Injection, SerDes Loopback,

and more.

Performa

The PEX 8712’s real time perfor

users to literally “see” ingress and egress performance on

each port as traffic passes through the switch using PLX’s

Software Development Kit (SDK). The monitoring is

completely passive and therefore has no affect on over

system performance. Internal counters provide extensive

granularity down to traffic & packet type and even allows

for the filtering of traffic (i.e. count only Memory Writes).

Users can evaluate their sys

physical layer using the PEX 8712’s SerDes Eye Captur

feature. Using PLX’s SDK, users can view the receiver

eye of any lane on the switch. Users can then modify

SerDes settings and see the impact on the receiver eye

Figure 5 shows a screenshot of the SerDes Eye Capture

feature in the SDK.

Figure 5. SerDes Eye Capture

PCIe Packet Generator

ledged PCIe Packet

raffic

The PEX 8712 features a full-f

Generator capable of creating programmable PCIe t

running at up to Gen 3 speeds and capable of saturating a

x16 link. Using PLX’s Software Development Kit

(www.plxtech.com/sdk), designers can create custo

traffic scripts for system bring-up and debug. Fully

integrated into the PEX 8712, the Packet Generator p

to be a very convenient on-chip debug tool. Furthermore,

the Packet Generator can be used to create PCIe traffic to

test and debug other devices on the system.

m

roves