PEX8605, PCI Express Gen 2 Switch, 4 Lanes, 4 Ports

© PLX Technology, www.plxtech.com

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8/17/2011, Version 1.1

Flexible Port Configurations

The PEX8605 flexible architecture supports a number of port

configurations as required by the target applications as shown in

figure 1 below.

Figure 1. Port Configurations

SerDes Power and Signal Management

The PEX8605 provides low power capability that is fully

compliant with the PCI Express power management

specification. In addition, the SerDes physical links can be

turned off when unused for even lower power. The PEX8605

supports software control of the SerDes outputs to allow

optimization of power and signal strength in a system. The PLX

SerDes implementation supports four levels of power – off, low,

typical, and high. The SerDes block also supports loop-back

modes and advanced reporting of error conditions, which

enables efficient debug and management of the entire system.

Port Arbitration and QoS

The PEX8605 switch supports hardware fixed Round-Robin

Ingress Port Arbitration. The PEX8605 also supports Eight

Traffic Classes (TCs) as defined in the PCIe specification.

Applications

Suitable for fan-out, consumer, control plane applications, and

embedded systems, PEX8605 is suited for a wide variety of form

factors and applications.

Fan-Out

The PEX8605 switch, with its flexible configurations, allows

user specific tuning to a variety of host-centric as well as peer-

to-peer applications.

Figure 2. Fan-in/out Usage

Figure 2 shows a typical fan-out design, where the processor

provides a PCI Express link that needs to be fanned into a larger

number of smaller ports for a variety of I/O functions, each with

different bandwidth requirements.

Multi-Function Printer

With its small footprint, the PEX8605 is ideal for consumer

applications. Figure 3 shows a multi-function printer block

diagram. The four ports in the PEX8605 provide connectivity

between the processor to up to three peripherals each via an x1

connection. In this usage model, the PEX8605 provides

connectivity to the processor as well as to the various ASICs.

Figure 3. Printer Block Diagram

Digital TV Tuner

An example of a digital TV tuner is shown in Figure 4. In this

example, the integrated SoC has a single PCIe connection. The

PEX8605 is used to provide connection to the USB 3.0 endpoint,

a gigabit Ethernet controller and a 3D graphics engine which are

used to connect to other consumer peripherals, to a high speed

home network and provide advanced graphics respectively.

Figure 4. Digital TV Tuner Fan-in/out Usage

Bandwidth Bridge

There are four PCIe lanes available in the PEX8605. Each one

can represent an individual port or alternatively two can be

joined to form a x2 port. A x2 port can provide double the

bandwidth of a x1 port when all lanes are operating at the same

data rates (all at 2.5GT/s or 5.0GT/s). In some instances, the

need to match the bandwidth between devices running at

PEX 8605

x1

x1

x1

x1

PEX 8605

x1

x2

x1

CPU

PEX 8605

PCIe

PCIe

PCIe

x1

x1

x1

x1

2.5 &5 GT/s

System

x1

PEX 8605

Processor

ASIC

ASIC

Eth

Scanner

Marking

Engine

x1

x1

x1

x1

SoC

Gbe

x1

x1

PEX 8605

USB3.0

3D

Engine

x1