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HT82J97E bảng dữ liệu(PDF) 21 Page - Holtek Semiconductor Inc |
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HT82J97E bảng dữ liệu(HTML) 21 Page - Holtek Semiconductor Inc |
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21 / 46 page ![]() HT82J97E Rev. 1.30 21 May 10, 2004 To Configure PWM Block The HT82J97E has two PWM outputs (PWM1 and PWM2), which are shared with PC2, PC3 and can be easily enabled or disabled by the PWM1_EN or PWM2_EN bit of PORT_PC (16H) respectively. Also there is a one 8-bit PWMBR (PWM Base Period Register, 18H) which defines both PWM output wave- form cycle period. PWM cycle period = 256 ´1/fSYS´(PWMBR+1), or 256 ´4/fSYS´(PWMBR+1) where 1/fSYS or 4/fSYS is defined by PWM_S bit of the PORT_PC (16H) For example if PWMBR = 17, 4/fSYS (T1) is selected and fSYS = 6MHz. So both output waveform cycle period is 256 ´4/6 ´(17+1) = about 3072ms (0.325kHz) Now user can easily define the corresponding PWM duty by configuring the PWM1DR (for PWM1) or PWM2DR (for PWM2) duty registers PWM1 duty (high pulse) = (PWM1DR+1)/256 ´100% PWM1 high pulse period = PWM1 duty ´PWM cycle pe- riod PWM1 Low pulse period = PWM cycle period-high pulse period PWM2 duty (high pulse) = (PWM2DR+1)/256 ´100% PWM2 high pulse period = PWM2 duty ´PWM cycle pe- riod PWM2 Low pulse period = PWM cycle period-high pulse period For example PWMBR=17, PWM1DR=63, 4/fSYS (T1) is selected and fSYS=6MHz PWM cycle period = 256 ´4/6´(17+1) = about 3072ms (0.325kHz) PWM1 duty = (63+1)/256 = 25% PWM1 high pulse period = 25% ´3072ms = 768ms PWM1 low pulse period = 3072 ms -768ms = 2304ms P W M H i g h P u l s e P W M C y c l e P e r i o d I/O Port Special Registers Definition · Port-A (12H) - PA Register Bits Labels Read/Write Option Functions PA (12H) 0 PA0 R/W ¾ I/O (R/W) has pull-low and pull-high ROM code option. Has falling edge wake-up ROM code option. 1 PA1 R/W ¾ I/O (R/W) has pull-low and pull-high option. Has falling edge wake-up option. 2 PA2 R/W ¾ I/O (R/W) has pull-low and pull-high option. Has falling edge and rising edge wake-up option. 3 PA3 R/W ¾ I/O (R/W) has pull-low and pull-high option. Has falling edge and rising edge wake-up option. 4 PA4 R/W ¾ I/O (R/W) has pull-high option. Has falling edge wake-up option. 5 PA5 R/W ¾ I/O (R/W) has pull-high option. Has falling edge wake-up option. 6 PA6 R/W ¾ I/O (R/W) has pull-high option. Has falling edge wake-up option. 7 PA7 R/W ¾ I/O (R/W) has pull-high option. Has falling edge wake-up option, pin-shared with timer in- put pin. · Port-A Control (13H) - PAC This port configure the input or output mode of Port-A |
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