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STV9212 bảng dữ liệu(PDF) 20 Page - STMicroelectronics

tên linh kiện STV9212
Giải thích chi tiết về linh kiện  Video Processor for CRT Monitors with PictureBooST
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STV9212 bảng dữ liệu(HTML) 20 Page - STMicroelectronics

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I²C-Bus Interface Specifications
STV9212
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3
I²C-Bus Interface Specifications
The device is compatible to general I²C-bus specification. Its slave write address is DCh.
Subaddress (Sad) auto-incrementing is not available. Only Write mode is supported. The control
register map is given in Table 4.
Bold weight denotes default values assumed at power-on reset. The power-on reset is effected
every time that the supply voltage on VCCA pin drops below VPORTH threshold (Refer to electrical
specifications).
In order to ensure compatibility with future devices, all “Reserved” bits are to be set to 0 once
uploaded by the control software.
Table 4: I²C-Bus Register Map
Sad
b7b6b5
b4b3b2b1b0
01
CRST
Reserved
1000
0000
02
BRIG
1000
0000
03
DRIVE1
Reserved
1000
0000
04
DRIVE2
Reserved
1000
0000
05
DRIVE3
Reserved
1000
0000
06
Reserved
BRIGRG
0000
0001
07
Reserved
OSDCRST
0000
1001
08
OCPTG
TST1
TST0
BCSC1
BCWDTH
BCEDGE
BCSC0
0:BLK
1:ICP
0:Normal
1:Test
0:Normal
1:Test
0:Trig mode
1:HS pulse
01
0:Rising
1:Falling
0:HS trig
1:BLK trig
09
ASTBY
ABLEN
Reserved
TST2
Reserved
MOD
SWBLK
BLKPOL
0:Normal
1:Standby
0:Bl. disable
1:Bl. enable
0
0:Test
1:Normal
0
0:DC
1:AC
0:Disable
1:Enable
0:Non-inv.
1:Inverted
0A
IBL1
1000
0000
0B
IBL2
1000
0000
0C
IBL3
1000
0000
0D
PASTBY
Reserved
TST4
TST3
BW
0:Normal
1:Standby
0
0:Normal
1:Test
0:Normal
1:Test
1000
0E
VIP
IBOF
IBLRG
0:0.2V
1:0.4V
100
000
0:Wide
1:Narrow
0F
PBGEN
PBINS
Reserved
PBCRST
Reserved
PBBRIG
0:Disable
1:Enable
0:PB Pin
1:Perman.
00
1001
10
PBVIVEN
PBVIVAM
Reserved
PBVIVTC
Reserved
0:Disable
1:Enable
010
1000



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