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PCA9546AD bảng dữ liệu(PDF) 7 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  4-channel I2C switch with reset
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PCA9546AD bảng dữ liệu(HTML) 7 Page - NXP Semiconductors

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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 6 April 2005
7 of 25
Philips Semiconductors
PCA9546A
4-channel I2C switch with reset
7.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tWL, the PCA9546A will reset its
registers and I2C-bus state machine and will deselect all channels. The RESET input must
be connected to VDD through a pull-up resistor.
7.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9546A in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9546A registers and I2C-bus state machine are initialized to their default
states—all zeroes—causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V to reset the device.
7.5 Voltage translation
The pass gate transistors of the PCA9546A are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this data
sheet). In order for the PCA9546A to act as a voltage translator, the Vo(sw) voltage should
be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9546A supply voltage is
3.5 V or lower, so the PCA9546A supply voltage could be set to 3.3 V. Pull-up resistors
can then be used to bring the bus voltages to their appropriate levels (see Figure 14).
(1) maximum
(2) typical
(3) minimum
Fig 7.
Pass gate voltage versus supply voltage
VDD (V)
2.0
5.5
4.5
3.0
4.0
002aaa964
3.0
2.0
4.0
5.0
Vo(sw)
(V)
1.0
3.5
5.0
2.5
(1)
(2)
(3)



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