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SSM3582BCPZ bảng dữ liệu(PDF) 8 Page - Analog Devices

tên linh kiện SSM3582BCPZ
Giải thích chi tiết về linh kiện  2횞, 31.76 W, Digital Input, Filterless Stereo Class-D Audio Amplifier
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SSM3582
Data Sheet
Rev. 0| Page 8 of 59
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT VOLTAGE1
BCLK, FSYNC, SDATA, SCL, and SDA Pins
High (VIH)
0.7 × DVDD
5.5
V
Low (VIL)
−0.3
+0.3 × DVDD
V
INPUT LEAKAGE
BCLK, FSYNC, SDATA, ADDRx, SCL, and SDA Pins
High (IIH)
1
μA
Low (IIL)
1
μA
INPUT CAPACITANCE
5
pF
OUTPUT DRIVE STRENGTH1
SDA
3
5
mA
SAMPLE RATE (FSYNC FREQUENCY)
8
192
kHz
1 The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.
DIGITAL TIMING SPECIFICATIONS
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 7.
Limit
Parameter
Min
Max
Unit
Description
I2C PORT
fSCL
400
kHz
SCL frequency
tSCLH
0.26
μs
SCL high
tSCLL
0.5
μs
SCL low
tSCS
0.26
μs
Setup time; relevant for repeated start condition
tSCH
0.26
μs
Hold time; after this period, the first clock is generated
tDS
50
ns
Data setup time
tDH
0.14
μs
Data hold time
tSCR
120
ns
SCL rise time
tSCF
120
ns
SCL fall time
tSDR
120
ns
SDA rise time
tSDF
120
ns
SDA fall time
tBFT
0.5
μs
Bus free time (time between stop and start)
DIGITAL INPUT TIMING SPECIFICATIONS
Table 8.
Limit
Parameter
TMIN
TMAX
Unit
Description
SERIAL PORT
tBIL
10
ns
BCLK low pulse width
tBIH
10
ns
BCLK high pulse width
tSIS
4
ns
SDATA setup; time to BCLK rising
tSIH
4
ns
SDATA hold; time from BCLK rising
tLIS
5
ns
FSYNC setup time to BCLK rising
tLIH
5
ns
FSYNC hold time to BCLK rising
tBP
20
ns
Minimum BCLK period



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