LTC4556EUF datasheet(13/20 Pages) LINER

13 / 20 page

LTC4556

4556f

10kV ESD Protection

All smart card pins (CLK, RST, I/O, C4, C8 and VCC) can

withstand over 10kV of human body model ESD in-situ. In

order to ensure proper ESD protection, careful board

layout is required. The GND pin should be tied directly

to a ground plane. The multilayer ceramic chip VCC capaci-

tor should be located very close to the VCC pin and tied

immediately to the ground plane.

Capacitor Selection

Warning: A polarized capacitor such as tantalum or alumi-

num should never be used for the flying capacitor since its

voltage can reverse upon start up of the LTC4556. Low

ESR ceramic capacitors should always be used for the

flying capacitor.

A total of four capacitors are required to operate the

LTC4556. An input bypass capacitor is required at VBATT

and DVCC. An output bypass capacitor is required on the

smart card VCC pin. A charge pump flying capacitor is

required from C+ to C– and a charge storage capacitor is

required on the charge pump out pin CPO.

To prevent excessive noise spikes due to charge pump

operation, low ESR (equivalent series resistance) multi-

layer ceramic chip capacitors are strongly recommended.

There are several types of ceramic capacitors available

each having considerably different characteristics. For

example, X7R/X5R ceramic capacitors have excellent volt-

age and temperature stability but relatively low packing

density. Y5V ceramic capacitors have apparently higher

packing density but poor performance over their rated

voltage or temperature ranges. Under certain voltage and

temperature conditions Y5V and X7R/X5R ceramic ca-

pacitors can be compared directly by case size rather than

specified value for a desired minimum capacitance.

Placement of the capacitors is critical for correct operation

of the LTC4556. Because the charge pump generates large

current steps, all of the capacitors should be placed as

close to the LTC4556 as possible. The low impedance

APPLICATIO S I FOR ATIO

nature of multilayer ceramic chip capacitors will minimize

voltage spikes but only if the power path is kept very short

(i.e., minimum inductance). The VBATT node should be

especially well bypassed. The capacitor for this node

should be directly adjacent to the QFN package. The CPO

and flying capacitors should be very close as well. The

LTC4556 can tolerate more distance between the LDO

capacitor and the VCC pin.

Figure 4 shows an example of a tight printed circuit board

layout using single layer copper. For best performance a

multilayer board can be used and should employ a solid

ground plane on at least one layer.

The following capacitors are recommended for use with

the LTC4556:

TYPE

VALUE

CASE SIZE

MURATA P/N

BATT, CPO,

X5R

µF

0603

GRM39 X5R 105K 6.3

CFLY, VCC

CDVCC

X5R

0.1

µF

0402

GRM36 X5R 104K 10

VCC

GND

VBATT

CPO

4556 F04

Figure 4. Optimum Single Layer PCB Layout

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