LTC1744 datasheet(13/24 Pages) LINER

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LTC1744

1744f

APPLICATIO S I FOR ATIO

given sampling capacitor size. The capacitors shown

attached to each input (CPARASITIC) are the summation of

all other capacitance associated with each input.

During the sample phase when ENC/ENC is low, the

transmission gate connects the analog inputs to the sam-

pling capacitors and they charge to and track the differen-

tial input voltage. When ENC/ENC transitions from low to

high the sampled input voltage is held on the sampling

capacitors. During the hold phase when ENC/ENC is high

the sampling capacitors are disconnected from the input

and the held voltage is passed to the ADC core for

processing. As ENC/ENC transitions from high to low the

inputs are reconnected to the sampling capacitors to

acquire a new sample. Since the sampling capacitors still

hold the previous sample, a charging glitch proportional to

the change in voltage between samples will be seen at this

time. If the change between the last sample and the new

sample is small the charging glitch seen at the input will be

small. If the input change is large, such as the change seen

with input frequencies near Nyquist, then a larger charging

glitch will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential

drive to achieve specified performance. Each input should

swing

±0.8V for the 3.2V range or ±0.5V for the 2V range,

around a common mode voltage of 2.5V. The VCM output

pin (Pin 2) may be used to provide the common mode bias

level. VCM can be tied directly to the center tap of a

transformer to set the DC input level or as a reference level

to an op amp differential driver circuit. The VCM pin must

be bypassed to ground close to the ADC with 4.7

µF or

greater.

Input Drive Impedance

As with all high performance, high speed ADCs the dy-

namic performance of the LTC1744 can be influenced by

the input drive circuitry, particularly the second and third

harmonics. Source impedance and input reactance can

influence SFDR. At the falling edge of encode the sample-

and-hold circuit will connect the 7pF sampling capacitor to

the input pin and start the sampling period. The sampling

period ends when encode rises, holding the sampled input

on the sampling capacitor. Ideally the input circuitry

should be fast enough to fully charge the sampling capaci-

tor during the sampling period 1/(2FENCODE); however,

this is not always possible and the incomplete settling may

degrade the SFDR. The sampling glitch has been designed

to be as linear as possible to minimize the effects of

incomplete settling.

For the best performance, it is recomended to have a

source impedence of 100

Ω or less for each input. The

source impedence should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Figure 2. Equivalent Input Circuit

CSAMPLE

7pF

CPARASITIC

8pF

CPARASITIC

8pF

VDD

LTC1744

AIN

1744 F02

CSAMPLE

7pF

BIAS

VDD

AIN

–

ENC

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