CY2DP314
Document #: 38-07550 Rev.*E
Page 2 of 9
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP314. The agency name and relevant specification is
listed below in Table 2.
Pin Definitions
Pin
Name
I/O
Type
Description
1,10,11,20,3
VCC
+PWR
Power
Power supply, positive connection
2NC
No connect
4
CLK_SEL
I,PD
LVCMOS
InPut Clock Select
5
CLKA
I,PD[1]
ECL/PECL
Default differential clock input
6
CLKA#
I, PD/PU
ECL/PECL
Default differential clock input
7
CLKB
I,PD
HSTL
Alternate differential clock input
8
CLKB#
I, PD/PU
HSTL
Alternate differential clock input
9
VEE[2]
–PWR
Power
Power supply, negative connection
18,16,14,12
Q[0:3]#
O
ECL/PECL
Complement output
19,17,15,13
Q[0:3]
O
ECL/PECL
True output
Table 1.
Control
Operation
CLK_SEL
0
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
1
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL-compatible signals with respective power configurations
Table 2.
Agency Name
Specification
JEDEC
JESD 020B (MSL)
JESD 8-6 (HSTL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode),
VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)
and are between VCC and VEE.
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