Preliminary Technical Data

AD5601/AD5611/AD5621

Rev. PrC | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TOP VIEW

(Not to Scale)

GND

SCLK

DIN

AD5601/

AD5611/

AD5621

SYNC

1

2

3

6

5

4

Figure 3. 6-Lead SC70 Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

SYNC

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow.

rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

2

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz.

3

DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

4

to GND.

5

GND

Ground Reference Point for All Circuitry on the AD5601/AD5611/AD5621.

6

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.