ADRF6518ACPZ-R7 datasheet(20/39 Pages) AD

tên linh kiện	ADRF6518ACPZ-R7

Giải thích chi tiết về linh kiện	1.1 GHz Variable Gain Amplifiers Baseband Programmable Filters

PDF	39 Pages

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20 / 39 page

ADRF6518

Data Sheet

Rev. A | Page 20 of 39

The filter frequency, amplifier gains, filter bypass mode, and

offset correction loops can be programmed using the SPI

interface. Table 5 provides the bit map for the internal 15-bit

Table 4. Filter Mode and Power Mode Options

Filter Bypass

Filter

VGA low power; filter off

VGA low power; filter low

power

VGA high power; filter

off

VGA low power; filter high

power

Table 5. Register Map

MSB

LSB

B15

B14

B13

B12

B11

B10

Filter frequency code and filter bypass mode

Power mode

Digital gain code

DC offset disable

Code = 1 dB corner in MHz

For example, 31 MHz = 011111 (MSB first)

Use 000000 for filter bypass mode

0: low power

1: high power

Use 1 for filter BW > 31 MHz, in

filter mode

Use 1 for channel BW > 60 MHz,

in filter bypass mode

VGA1 gain

00: 15 dB

01: 12 dB

10: 9 dB

11: 9 dB

VGA2 gain

00: 21 dB

01: 18 dB

10: 15 dB

11: 12 dB

VGA3 gain

00: 21 dB

01: 18 dB

10: 15 dB

11: 12 dB

Postamp

0: 3 dB

1: 9 dB

0: enable

1: disable

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