SH7145F-ZTAT datasheet(49/773 Pages) RENESAS

49 / 773 page

Rev. 2.0, 09/02, page 9 of 732

Type

Symbol

I/O

Name

Function

WRH

Output

Write

upper half

Shows writing into the upper 8 bits (bits 15

to 8) of the external data.

WRL

Output

Write lower

half

Shows writing into the lower 8 bits (bit7 to

bit0) of the external data.

Bus control

WAIT

Input

Wait

Inserts the wait cycles into the bus cycle

when accessing the external spaces.

DREQ0

DREQ1

Input

DMA transfer

request

DMA request input pins from an external

device.

DRAK0

DRAK1

Output

DREQ request

acknowledge

Outputs an acknowledge signal to the

external device that has input a DMA

transfer request signal.

Direct

memory

access

controller

(DMAC)

DACK0

DACK1

Output

DMA transfer

strobe

Outputs a strobe to the I/O of the external

device that has input a DMA transfer

request signal.

TCLKA

TCLKB

TCLKC

TCLKD

Input

External clock

input for MTU

timer

These pins input an external clock.

TIOC0A

TIOC0B

TIOC0C

TIOC0D

Input/

Output

MTU input

capture/output

compare

(channel 0)

The TGRA_0 to TGRD_0 input capture

input/output compare output/PWM output

pins.

TIOC1A

TIOC1B

Input/

Output

MTU input

capture/output

compare

(channel 1)

The TGRA_1 to TGRB_1 input capture

input/output compare output/PWM output

pins.

TIOC2A

TIOC2B

Input/

Output

MTU input

capture/output

compare

(channel 2)

The TGRA_2 to TGRB_2 input capture

input/output compare output/PWM output

pins.

TIOC3A

TIOC3B

TIOC3C

TIOC3D

Input/

Output

MTU input

capture/output

compare

(channel 3)

The TGRA_3 to TGRD_3 input capture

input/output compare output/PWM output

pins.

Multi function

timer-pulse

unit (MTU)

TIOC4A

TIOC4B

TIOC4C

TIOC4D

Input/

Output

MTU input

capture/output

compare

(channel 4)

The TGRA_4 to TGRB_4 input capture

input/output compare output/PWM output

pins.

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