X98021 datasheet(6/29 Pages) RENESAS

tên linh kiện	X98021

Giải thích chi tiết về linh kiện	210MHz Triple Video Digitizer with Digital PLL

PDF	29 Pages

Scroll/Zoom	100%

nhà sản xuất	RENESAS [Renesas Technology Corp]

Trang chủ	http://www.renesas.com

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6 / 29 page

X98021

FN8219 Rev 3.00

Page 6 of 29

March 8, 2006

DATACLK

tSETUP

tHOLD

DATACLK

Pixel Data

FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING

Programmable

Width and Polarity

Analog

Video In

P/GP/BP[7:0]

OUT

8.5 DATACLK Pipeline Latency

S/GS/BS[7:0]

HSYNC

The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.

The sampling phase setting determines its relative position to the rest of the AFE’s output signals

DATACLK

HSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL

FIGURE 3. 24 BIT OUTPUT MODE

Programmable

Width and Polarity

Analog

Video In

OUT

8.5 DATACLK Pipeline Latency

HSYNC

The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.

The sampling phase setting determines its relative position to the rest of the AFE’s output signals

DATACLK

0 (Yo)

1 (Y1)G2 (Y2)

0 (Uo)R1 (V1)B2 (U2)

P[7:0]

HSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL

FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)

X98021 bảng dữ liệu(PDF) 6 Page - Renesas Technology Corp