PIC18F8720 datasheet(13/366 Pages) MICROCHIP

13 / 366 page

 2003 Microchip Technology Inc.

Advance Information

DS39609A-page 11

PIC18FXX20

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

MCLR/VPP

MCLR

VPP

Master Clear (input) or programming

voltage (output).

Master Clear (RESET) input. This pin is

an active low RESET to the device.

Programming voltage input.

OSC1/CLKI

OSC1

CLKI

CMOS/ST

CMOS

Oscillator crystal or external clock input.

Oscillator crystal input or external clock

source input. ST buffer when configured

in RC mode. Otherwise CMOS.

External clock source input. Always

associated with pin function OSC1 (see

OSC1/CLKI, OSC2/CLKO pins).

OSC2/CLKO/RA6

OSC2

CLKO

RA6

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output.

Connects to crystal or resonator in

Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO,

which has 1/4 the frequency of OSC1

and denotes the instruction cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X20 devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

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