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S34MS08G2 bảng dữ liệu(PDF) 13 Page - Cypress Semiconductor |
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S34MS08G2 bảng dữ liệu(HTML) 13 Page - Cypress Semiconductor |
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13 / 17 page ![]() Document Number: 002-00515 Rev. *G Page 13 of 17 S34MS08G2 8.3 Pin Capacitance Note 16. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips]. 8.4 Power Consumptions and Pin Capacitance for Allowed Stacking Configurations When multiple dies are stacked in the same package, the power consumption of the stack will increase according to the number of chips. As an example, the standby current is the sum of the standby currents of all the chips, while the active power consumption depends on the number of chips concurrently executing different operations. When multiple dies are stacked in the same package the pin/ball capacitance for the single input and the single input/output of the combo package must be calculated based on the number of chips sharing that input or that pin/ball. Table 8. Pin Capacitance (TA = 25°C, f=1.0 MHz) Parameter Symbol Test Condition Min Max Unit Input CIN VIN = 0V — 10 pF Input / Output CIO VIL = 0V — 10 |
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