EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

13

01/31/2004

V4.7

R7 (PORT7 I/O data, Data RAM bank)

PAGE0 (PORT7 I/O data register)

7

6

5

4

3

2

1

0

P77

P76

P75

P74

P73

P72

P71

P70

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7(0~7) I/O data register

User can use IOC register to define input or output each bit.

PAGE1 (CTCSS detection output, Data RAM bank selection bits)

7

6

5

4

3

2

1

0

-

DETO

-

-

-

-

RAM_B1

RAM_B0

R

R/W-0

R/W-0

Bit 0 ~ Bit1 (RAM_B0 ~ RAM_B1) : Data RAM bank selection bits

Each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes RAM size.

Data RAM bank selection : (Total RAM = 1.0K)

RAM_B1

RAM_B0

RAM bank

0

0

Bank0

0

1

Bank1

1

0

Bank2

1

1

Bank3

Bit 2 ~ Bit 5 : (undefined) not allowed to use

Bit 6(DETO) : CTCSS tone detection

The signal passing CTCSS sub audio LPF will be extracted CTCSS tone. Then this tone will go into the

ZC(Zero-crossing detector) and output to DETO bit. This bit reflects the CTCSS tone frequency pulse

waveform. The user can count the timing to get the CTCSS frequency. Also see IOCE PAGE1 for CTCSS

block and switch control.

Bit 7 : (undefined) not allowed to use

R8 (PORT8 I/O data, Data RAM address)

PAGE0 (PORT8 I/O data register)

7

6

5

4

3

2

1

0

P87

P86

P85

P84

P83

P82

P81

P80

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8(0~7) I/O data register

User can use IOC register to define input or output each bit.

PAGE1 (Data RAM address register)

7

6

5

4

3

2

1

0

RAM_A7 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address

The data RAM bank’s selection is from R7 PAGE1 bit0 ~ bit 1 (RAM_B0 ~ RAM_B1).

R9 (PORT9 I/O data, Data RAM data buffer)

PAGE0 (PORT9 I/O data register)

7

6

5

4

3

2

1

0

P97

P96

P95

P94

P93

P92

P91

P90

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W