ISL97652 datasheet(13/25 Pages) RENESAS

13 / 25 page

ISL97652

FN9287 Rev 1.00

Page 13 of 25

November 2, 2007

Rectifier Diode (Boost Converter)

A high-speed diode is necessary due to the high switching

frequency. Schottky diodes are recommended because of their

fast recovery time and low forward voltage. The reverse

voltage rating of this diode should be higher than the maximum

output voltage. The rectifier diode must meet the output current

and peak inductor current requirements. The following table is

some recommendations for boost converter diode.

Output Capacitor

The output capacitor supplies the load directly and reduces the

ripple voltage at the output. Output ripple voltage consists of two

components: the voltage drop due to the inductor ripple current

flowing through the ESR of output capacitor, and the charging

and discharging of the output capacitor.

For low ESR ceramic capacitors, the output ripple is dominated

by the charging and discharging of the output capacitor. The

voltage rating of the output capacitor should be greater than

the maximum output voltage.

Note: Capacitors have a voltage coefficient that makes their

effective capacitance drop as the voltage across then

increases. COUT in Equation 7 above assumes the effective

value of the capacitor at a particular voltage and not the

manufacturer's stated value, measured at zero volts.

The following table shows some selections of output

capacitors.

Loop Compensation (Boost Converter)

The boost converter of ISL97652 can be compensated by a

RC network connected from VC pin to ground. CC = 4.7nF and

RC = 10k RC network is used in the demo board. A higher

resistor value can be used to lower the transient load change

AVDD overshoot - however, this may be at the expense of

stability to the loop.

The stability can be examined by repeatedly changing the load

between 100mA and a max level that is likely to be used in the

system being used. The AVDD voltage should be examined

with an oscilloscope set to AC 100mV/div and the amount of

ringing observed when the load current changes. Reduce

excessive ringing by reducing the value of the resistor in series

with the VC pin capacitor.

AVDD Delay Switch

The ISL97652 integrates a PMOS disconnect switch for the

AVDD boost output to disconnect VIN from AVDD when the EN2

input is not selected. When EN2 is taken high, the PMOS FET

is turned on to connect power to the display. The CSUI

capacitor provide soft-start control for the connection of this

switch.

The operation of the AVDD delay switch is controlled by

internal VDSOK and VDSHYS control signals which operate as

follows:

During start-up (or during fault conditions):

VDSOK goes to 1 when V(SWI - SWO) becomes less than

~0.5V. This will turn-on the boost function.

VDSOK goes to 0 when VDS_pfet becomes greater than

~1.1V. This will turn-off the boost function.

The threshold voltages have a Vin dependence such that:

For Vin1 = 8V: VDSOK goes to 1 occurs at ~0.5V and VDSOK

goes to 0 occurs at ~1.1V.

For Vin1 =18.5V: VDSOK goes to1 occurs at ~1.13V and

VDSOK goes to 0 occurs at ~2.65V.

V(SWI - SWO) is the VDS voltage across the internal PFET

protection switch. If this voltage exceeds 1.1V for some reason

(e.g. under fault conditions or during start-up if VMAIN rises

faster than AVDD) the boost is turned-off to allow the AVDD

(SWO) potential to catch-up with VMAIN (SWI).

VDSHYS is the VDS hysteresis level;

Once VDSOK goes to 1 the voltage V(SWI - SWO) then needs

to exceed 1.1V for VDSOK goes to 0.

During normal operation VDS will be ~Ron_PFET * Iload

(~ 0.18x2 = 0.36V for max AVDD load).

If a fault develops on AVDD, which causes VDS to exceed

1.1V, then the boost operation is interrupted by the internal

VDSOK goes to 0 signal and fault timers will start to operate

while the rising/falling character of AVDD is monitored.

AVDD Delay Switch Fault Operation

When enabled, the gate of the PFET is pulled down with a

30µA current, turning on the FET switch. The speed of this

turn-on can be controlled by placing a capacitor from SWI to

SUI. In normal operation the gate (and SUI pin) are pulled

down to 5V below SWI. The AVDD delay switch circuitry

constantly monitors both the current in the switch and the

voltage at SWO. If the current exceeds the current limit of 2A,

the gate of the FET (and also the SUI pin) will be pulled up to

the correct level to limit the current to 2A. In this mode the

switch acts like a 2A current source. this current cannot be

maintained indefinitely due to the power dissipation on chip.

Therefore, three separate fault mechanisms are operated.

TABLE 4. BOOST CONVERTER RECTIFIER DIODE

RECOMMENDATION

DIODE

VR/IAVG

RATING

PACKAGE

VENDOR

SS23

30V/2A

SMB

Fairchild Semiconductor

SL23

30V/2A

SMB

Vishay Semiconductor

TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION

CAPACITOR

SIZE

VENDOR

PART NUMBER

10µF/25V

1210

TDK

C3225X7R1E106M

10µF/25V

1210

Murata

GRM32DR61E106K

VRIPPLE

ILPK ESR

VO VIN

–

------------------------

CAVDD

--------------------

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

(EQ. 7)

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