EL4093

FN7159 Rev 0.00

Page 8 of 12

January 1996

Figure 1 shows how the two are connected to provide this

function; the S/H compares the output of the CFA to a DC

reference, and any difference between them causes an output

current from the S/H. This “autozero” current is fed to the CFA

inverting input, the effect of which is to move the CFA output

towards the reference voltage. This autozero mechanism

The autozero mechanism is typically active for only a short

period of each video line. Figure 2 shows a NTSC video signal

along with the EL4581 back porch output. The back porch

signal is used to drive the HOLD input of the EL4093, and we

see that the EL4093 is in sample mode for only 3.5µs of each

line. It is during this time that the autozero mechanism

attempts to drive the CFA output towards the reference

voltage, at the same time putting a correction voltage onto the

EL4093 is in hold mode, but DC correction is maintained by the

Power Supply Bypassing and Printed Circuit Board

Layout

As with any high frequency device, good printed circuit board

layout is necessary for optimum performance. Ground plane

construction is highly recommended. Lead lengths should be

as short as possible. The power supply pins must be well

bypassed to reduce the risk of oscillation. In the EL4093 there

are two sets of supply pins: V+1/V-1 provide power for the

CFA, and V+2/V-2 are for the S/H amplifier. Good performance

can be achieved using only one set of bypass capacitors,

although they must be close to the V+1/V-1 pins since that is

where the high frequency currents flow. The combination of a

4.7µF tantalum capacitor in parallel with a 0.01µF capacitor

has been shown to work well. Chip capacitors are

recommended for the 0.01µF bypass to minimize lead

inductance.

For good AC performance, parasitic capacitance should be

kept to a minimum, especially at the CFA inverting input.

Ground plane construction should be used, but it should be

removed from the area near the inverting input to minimize any

stray capacitance at that node. Chip resistors are

avoided if possible. Sockets add parasitic inductance and

capacitance which will result in some additional peaking and

overshoot.

If the CFA is configured for non-inverting gain, then one should

also pay attention to the trace leading to the +input. The

inductance of a long trace (> 3’) can form a resonant network

with the amplifier input, resulting in high frequency oscillations

around 700MHz. In such cases a 50

–100 series resistor

placed close to the +input would isolate this inductance and

damp out the resonance.

Capacitance at the Inverting Input

Any manufacturer’s high-speed voltage or current feedback

amplifier can be affected by stray capacitance at the inverting

input. For inverting gains this parasitic capacitance has little

effect because the inverting input is a virtual ground, but for

non-inverting gains this capacitance (in conjunction with the

feedback and gain resistors) creates a pole in the feedback

path of the amplifier. This pole, if low enough in frequency, has

the same destabilizing effect as a zero in the forward open-

loop response. Hence it is important to minimize the stray

capacitance at this node by removing the nearby ground plane.

In addition, since the S/H output connects to this node, it is

important to minimize the trace capacitance. Good practice

here would be to connect the two pins with a short trace

directly underneath the chip.

Feedback Resistor Values

The EL4093 has been optimized for a gain of +2 with

bandwidth of 300MHz at a gain of +2 driving a 150

 load.

Since the amplifier inside the EL4093 uses current mode

bandwidth. Shown in the table below are optimum feedback

resistor values for different closed loop gains.

FIGURE 1.

FIGURE 2.

GAIN

OPTIMUM RF

BW (MHz)

PEAKING (dB)

+1

910

314

0.2